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https://github.com/VLSIDA/OpenRAM.git
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Matt Guthaus
63d0523228
Added scn4m_subm files (instead of scn4me_subm). Fixed missing cifoutput/cifinput in magic tech file and gds files. Fixed incorrect M3/via3/M4 design rules.
15 lines
452 B
SourcePawn
15 lines
452 B
SourcePawn
*********************** tri_gate ******************************
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.SUBCKT tri_gate in out en en_bar vdd gnd
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* SPICE3 file created from tri_gate.ext - technology: scmos
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M1000 vdd in a_16_108# vdd p w=1.6u l=0.4u
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M1001 a_76_212# a_16_108# vdd vdd p w=1.6u l=0.4u
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M1002 out en_bar a_76_212# vdd p w=1.6u l=0.4u
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M1003 gnd in a_16_108# gnd n w=0.8u l=0.4u
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M1004 a_76_108# a_16_108# gnd gnd n w=0.8u l=0.4u
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M1005 out en a_76_108# gnd n w=0.8u l=0.4u
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.ENDS
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