mirror of https://github.com/VLSIDA/OpenRAM.git
150 lines
5.2 KiB
Markdown
150 lines
5.2 KiB
Markdown
### [Go Back](./index.md#table-of-contents)
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# Debugging and Unit Testing
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This page of the documentation explains the debugging and unit testing of
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OpenRAM.
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## Table of Contents
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1. [Unit Tests](#unit-tests)
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1. [Unit Test Organization](#unit-test-organization)
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1. [Running Unit Tests](#running-unit-tests)
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1. [Successful Unit Tests](#successful-unit-tests)
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1. [Debugging Unsuccessful Unit Tests](#debugging-unsuccessful-unit-tests-or-sram_compilerpy)
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1. [Temporary Output Files](#temporary-output-files)
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## Unit Tests
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OpenRAM has the set of thorough regression tests implemented with the Python
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unit test framework:
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* Unit tests allow users to add features without worrying about breaking
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functionality.
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* Unit tests guide users when porting to new technologies.
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* Every sub-module has its own regression test.
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* There are regression tests for memory functionality, library cell
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verification, timing verification, and technology verification.
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## Unit Test Organization
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* `00_code_format_test.py` does basic lint checking.
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* `01_library_drc_test.py` checks DRC of all library cells for the technology.
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* `02_library_lvs_test.py` checks LVS of all library cells for the technology.
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* `03_*_test.py` checks DRC and LVS of wires and transistors classes.
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* `04_*_test.py` checks DRC and LVS of parameterized cells.
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* `05-19_*_test.py` checks DRC and LVS of module cells (moving upward in hierarchy with numbers)
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* `20_*_test.py` check DRC and LVS of full SRAM layouts with various configurations.
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* `21_*_test.py` checks timing of full SRAMs and compares (with tolerance) to precomputed result.
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> **Note**: These tests may fail using different simulators due to the tolerance level.
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* `22_*_test.py` checks functional simulation of full SRAMs with various configurations.
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* `23-25_*_test.py` checks lib, lef, and verilog outputs using diff.
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* `30_openram_test.py` checks command-line interface and whether output files are created.
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## Setup
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Before running any unit tests, make sure to install OpenRAM.
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> See [Python library](./python_library.md#go-back) for details.
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If you have the library already installed and `OPENRAM_HOME` set, the library will use the installation on the `OPENRAM_HOME` path.
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## Running Unit Tests
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Regression testing performs a number of tests for all modules in OpenRAM. From
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the unit test directory (`$OPENRAM_HOME/tests`), use the following command to run
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all regression tests:
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```
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cd OpenRAM/compiler/tests
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make -j 3
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```
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The `-j` can run with 3 threads. By default, this will run in all technologies.
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> **Note**: If you have not run openram before running unit tests, the conda
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> environment will not be installed. You can install it by running
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> `OpenRAM/install_conda.sh` (see [Basic Setup](basic_setup.md#anaconda) for
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> more details).
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To run a specific test in all technologies:
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```
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cd OpenRAM/compiler/tests
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make 05_bitcell_array_test
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```
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To run a specific technology:
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```
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cd OpenRAM/compiler/tests
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TECHS=scn4m_subm make 05_bitcell_array_test
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```
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To increase the verbosity of the test, add one (or more) `-v` options and pass
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it as an argument to OpenRAM:
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```
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ARGS="-v" make 05_bitcell_array_test
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```
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Unit test results are put in a directory:
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```
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OpenRAM/compiler/tests/results/<technology>/<test>
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```
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If the test fails, there will be a `tmp` directory with intermediate results. If
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the test passes, this directory will be deleted to save space. You can view the
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`.out` file to see what the output of a test is in either case.
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To preserve results on successful tests (done automatically if test fails):
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```
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KEEP=1 make 05_bitcell_array_test
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```
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## Successful Unit Tests
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```console
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user@host:/openram/compiler/tests$ make
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scn4m_subm/12_tri_gate_array_test ... PASS!
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scn4m_subm/19_pmulti_bank_test ... PASS!
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freepdk45/21_ngspice_delay_global_test ... PASS!
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scn4m_subm/23_lib_sram_linear_regression_test ... PASS!
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.
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.
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.
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```
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```console
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user@host:/openram/compiler/tests$ make 01_library_test
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scn4m_subm/01_library_test ... PASS!
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freepdk45/01_library_test ... PASS!
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```
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## Debugging Unsuccessful Unit Tests (or sram\_compiler.py)
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* You will get a FAIL during unit test
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* You can see the output and stack trace in
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`$OPENRAM_HOME/tests/results/<tech>/<test>.out`
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* Examine the temporary output files in the temp directory
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(`$OPENRAM_HOME/tests/results/<tech>/<test>/`)
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```console
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user@host:/openram/compiler/tests$ make 01_library_test
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scn4m_subm/01_library_test ... FAIL!
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```
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### It didn't finish... where are my files?
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* OpenRAM puts all temporary files in a temporary directory named:
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* `$OPENRAM_HOME/tests/results/<tech>/<test>/`
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* This allows multiple unit tests to simultaneously run
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* After a successful run, the directory and contents are deleted
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* To preserve the contents, you can run with the `KEEP` option for debugging
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## Temporary Output Files
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* DRC standard output (`*.drc.out`), errors (`*.drc.err`), and results (`*.drc.results`)
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* LVS standard output (`*.lvs.out`), errors (`*.lvs.out`), and results (`*.lvs.results`)
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* GDS (and Magic) files for intermediate modules (`temp.gds`, `temp.mag`)
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* SPICE netlist for intermediate module results (`temp.sp`)
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* Extracted layout netlist for intermediate module results (`extracted.sp`)
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* Magic only: Run scripts for DRC (`run_drc.sh`) and LVS (`run_lvs.sh`)
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* Calibre only: Runset file for DRC (`drc_runset`) and LVS (`lvs_runset`)
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