OpenRAM/compiler/pgates
Matt Guthaus 19d46f5954 Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
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pbitcell.py Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
pgate.py Add dffs to control logic. Rename layout pin segment/rect functions for consistency. Redo gnd/vdd pins in control. 2018-03-23 08:14:09 -07:00
pinv.py Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
pinvbuf.py Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
pnand2.py Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
pnand3.py Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
pnor2.py Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
precharge.py Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
ptx.py Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00
single_level_column_mux.py Finalized separation of netlist/layout creation. 2018-08-27 14:18:32 -07:00