Hunter Nichols 8b6a28b6fd Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.

2018-11-13 22:24:18 -08:00

..

bank_select.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

bank.py

Merged with dev. Fixed merge conflict.

2018-11-09 17:18:19 -08:00

bitcell_array.py

Added initial code for determining the logical effort delay of the wordline.

2018-11-08 23:54:18 -08:00

control_logic.py

Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.

2018-11-13 22:24:18 -08:00

delay_chain.py

Added sense amp enable delay calculation.

2018-11-08 23:54:18 -08:00

dff_array.py

Added initial code for determining the logical effort delay of the wordline.

2018-11-08 23:54:18 -08:00

dff_buf_array.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

dff_buf.py

Clean up new code for add_modules, add_pins and netlist/layouts.

2018-08-28 10:24:09 -07:00

dff_inv_array.py

Added initial code for determining the logical effort delay of the wordline.

2018-11-08 23:54:18 -08:00

dff_inv.py

Added initial code for determining the logical effort delay of the wordline.

2018-11-08 23:54:18 -08:00

dff.py

Added initial code for determining the logical effort delay of the wordline.

2018-11-08 23:54:18 -08:00

hierarchical_decoder.py

Move power pins in hierarchical decoder to be further. Strap rails instead for redundant vias.

2018-10-20 12:54:12 -07:00

hierarchical_predecode2x4.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

hierarchical_predecode3x8.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

hierarchical_predecode.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

multibank.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

precharge_array.py

Added sense amp enable delay calculation.

2018-11-08 23:54:18 -08:00

replica_bitline.py

Merged with dev. Fixed merge conflict.

2018-11-09 17:18:19 -08:00

sense_amp_array.py

Added sense amp enable delay calculation.

2018-11-08 23:54:18 -08:00

sense_amp.py

Merged with dev. Fixed merge conflict.

2018-11-09 17:18:19 -08:00

single_level_column_mux_array.py

Change default col mux size to 2. Add some comments.

2018-11-07 15:43:08 -08:00

tri_gate_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

tri_gate.py

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00

wordline_driver.py

Added initial code for determining the logical effort delay of the wordline.

2018-11-08 23:54:18 -08:00

write_driver_array.py

Update all drc usages to call function type

2018-10-12 14:37:51 -07:00

write_driver.py

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00