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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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80bc5b49c18f8cc5e0a910d306a7e27e7a6afab1
OpenRAM/compiler/characterizer
T
History
Hunter Nichols 8b6a28b6fd Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.
2018-11-13 22:24:18 -08:00
..
__init__.py
Fix check for missing simulator type in characterizer
2018-10-25 09:08:56 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Convert port index lists to three simple lists.
2018-11-08 12:19:40 -08:00
functional.py
Changed scmos bitcell 1rw,1r to have same tx widths as pbitcell.
2018-11-13 22:24:18 -08:00
lib.py
Fixed small bugs with new port index stuff and layout.
2018-11-08 17:40:22 -08:00
logical_effort.py
Added delay chain resizing based on analytical delay.
2018-11-09 17:14:52 -08:00
setup_hold.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
simulation.py
Convert port index lists to three simple lists.
2018-11-08 12:19:40 -08:00
stimuli.py
Add ngspice equivalents of RUNLVL
2018-10-24 10:31:27 -07:00
trim_spice.py
Fixed merge conflicts with sram.py
2018-10-22 17:29:14 -07:00
worst_case.py
Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation
2018-10-09 17:44:28 -07:00
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