mirror of https://github.com/VLSIDA/OpenRAM.git
134 lines
5.1 KiB
Python
134 lines
5.1 KiB
Python
import design
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from tech import drc
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from vector import vector
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import debug
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from globals import OPTS
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class sense_amp_array(design.design):
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"""
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Array of sense amplifiers to read the bitlines through the column mux.
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Dynamically generated sense amp array for all bitlines.
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"""
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def __init__(self, word_size, words_per_row):
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design.design.__init__(self, "sense_amp_array")
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debug.info(1, "Creating {0}".format(self.name))
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c = reload(__import__(OPTS.config.sense_amp))
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self.mod_sense_amp = getattr(c, OPTS.config.sense_amp)
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self.sense_amp_chars = self.mod_sense_amp.chars
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self.word_size = word_size
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self.words_per_row = words_per_row
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self.add_pins()
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self.create_layout()
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self.DRC_LVS()
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def add_pins(self):
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if (self.words_per_row == 1):
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for i in range(self.word_size):
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self.add_pin("bl[{0}]".format(i))
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self.add_pin("br[{0}]".format(i))
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else:
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for i in range(self.word_size):
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index = i * self.words_per_row
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self.add_pin("bl_out[{0}]".format(index))
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self.add_pin("br_out[{0}]".format(index))
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for i in range(self.word_size):
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self.add_pin("data_out[{0}]".format(i))
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self.add_pin("sclk")
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self.add_pin("vdd")
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self.add_pin("gnd")
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def create_layout(self):
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self.create_sense_amp()
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self.setup_layout_constants()
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self.add_sense_amp()
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self.connect_rails()
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self.offset_all_coordinates()
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def setup_layout_constants(self):
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self.vdd_positions = []
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self.gnd_positions = []
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self.SCLK_positions = []
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self.amp_positions = []
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self.Data_out_positions = []
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self.height = self.amp.height
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self.width = self.amp.width * self.word_size * self.words_per_row
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def create_sense_amp(self):
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self.amp = self.mod_sense_amp("sense_amp")
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self.add_mod(self.amp)
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def add_sense_amp(self):
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for i in range(self.word_size):
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name = "sa_d{0}".format(i)
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index = i * self.words_per_row
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amp_position = vector(self.amp.width * index, 0)
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BL_offset = amp_position + vector(self.sense_amp_chars["BL"][0], 0)
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BR_offset = amp_position + vector(self.sense_amp_chars["BR"][0], 0)
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self.add_inst(name=name,
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mod=self.amp,
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offset=amp_position)
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self.amp_positions.append(amp_position)
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if (self.words_per_row == 1):
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self.add_label(text="bl[{0}]".format(i),
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layer="metal2",
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offset=BL_offset)
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self.add_label(text="br[{0}]".format(i),
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layer="metal2",
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offset=BR_offset)
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self.connect_inst(["bl[{0}]".format(i),"br[{0}]".format(i),
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"data_out[{0}]".format(i),
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"sclk", "vdd", "gnd"])
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else:
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self.add_label(text="bl_out[{0}]".format(index),
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layer="metal2",
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offset=BL_offset)
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self.add_label(text="br_out[{0}]".format(index),
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layer="metal2",
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offset=BR_offset)
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self.connect_inst(["bl_out[{0}]".format(index), "br_out[{0}]".format(index),
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"data_out[{0}]".format(i),
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"sclk", "vdd", "gnd"])
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self.add_label(text="data_out[{0}]".format(i),
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layer="metal2",
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offset=amp_position + self.sense_amp_chars["Dout"])
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self.Data_out_positions.append(amp_position + self.sense_amp_chars["Dout"])
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def connect_rails(self):
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base_offset = vector(0, - 0.5 * drc["minwidth_metal1"])
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# add vdd rail across entire array
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vdd_offset = base_offset + vector(self.sense_amp_chars["vdd"]).scale(0,1)
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_offset,
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width=self.width,
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height=drc["minwidth_metal1"])
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self.vdd_positions.append(vdd_offset)
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# NOTE:the gnd rails are vertical so it is not connected horizontally
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# add gnd rail across entire array
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gnd_offset = base_offset + vector(self.sense_amp_chars["gnd"]).scale(0,1)
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_offset,
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width=self.width,
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height=drc["minwidth_metal1"])
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self.gnd_positions.append(gnd_offset)
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# add sclk rail across entire array
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sclk_offset = base_offset + vector(self.sense_amp_chars["SCLK"]).scale(0,1)
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self.add_layout_pin(text="sclk",
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layer="metal1",
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offset=sclk_offset,
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width=self.width,
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height=drc["minwidth_metal1"])
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self.SCLK_positions.append(sclk_offset)
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