mirror of https://github.com/VLSIDA/OpenRAM.git
534 lines
24 KiB
Python
534 lines
24 KiB
Python
import contact
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import design
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import debug
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from tech import drc
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from ptx import ptx
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from vector import vector
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from globals import OPTS
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class nand_3(design.design):
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"""
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This module generates gds of a parametrically sized 3_input nand.
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This model use ptx to generate a 3_input nand within a cetrain height.
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The 3_input nand's cell_height should be the same as the 6t library cell.
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This module doesn't generate multi_finger 3_input nand gate,
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It generate only the minimum size 3_input nand gate
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"""
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c = reload(__import__(OPTS.config.bitcell))
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bitcell = getattr(c, OPTS.config.bitcell)
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def __init__(self, name, nmos_width=1, height=bitcell.chars["height"]):
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"""Constructor : Creates a pcell for a simple 3_input nand"""
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design.design.__init__(self, name)
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debug.info(2, "create nand_3 strcuture {0} with size of {1}".format(name, nmos_width))
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self.nmos_width = nmos_width
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self.height = height
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self.add_pins()
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self.create_layout()
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self.DRC_LVS()
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def add_pins(self):
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""" add pics for this module """
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self.add_pin_list(["A", "B", "C", "Z", "vdd", "gnd"])
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def create_layout(self):
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""" create layout """
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self.determine_sizes()
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self.create_ptx()
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self.setup_layout_constants()
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self.add_rails()
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self.add_ptx()
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self.add_well_contacts()
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# These aren't for instantiating, but we use them to get the dimensions
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self.poly_contact = contact.contact(("poly", "contact", "metal1"))
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self.m1m2_via = contact.contact(("metal1", "via1", "metal2"))
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self.connect_tx()
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self.connect_well_contacts()
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self.extend_wells()
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self.extend_active()
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self.connect_rails()
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self.route_pins()
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self.setup_layout_offsets()
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def determine_sizes(self):
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""" Determine the size of the transistors used in this module """
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self.nmos_size = self.nmos_width
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self.pmos_size = 2 * self.nmos_width / 3
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self.tx_mults = 1
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def create_ptx(self):
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""" Create ptx but not yet placed"""
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self.nmos1 = ptx(name="nand_3_nmos1",
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width=self.nmos_size,
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mults=self.tx_mults,
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tx_type="nmos")
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self.add_mod(self.nmos1)
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self.nmos2 = ptx(name="nand_3_nmos2",
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width=self.nmos_size,
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mults=self.tx_mults,
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tx_type="nmos")
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self.add_mod(self.nmos2)
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self.nmos3 = ptx(name="nand_3_nmos3",
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width=self.nmos_size,
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mults=self.tx_mults,
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tx_type="nmos")
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self.add_mod(self.nmos3)
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self.pmos1 = ptx(name="nand_3_pmos1",
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width=self.pmos_size,
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mults=self.tx_mults,
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tx_type="pmos")
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self.add_mod(self.pmos1)
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self.pmos2 = ptx(name="nand_3_pmos2",
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width=self.pmos_size,
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mults=self.tx_mults,
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tx_type="pmos")
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self.add_mod(self.pmos2)
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self.pmos3 = ptx(name="nand_3_pmos3",
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width=self.pmos_size,
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mults=self.tx_mults,
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tx_type="pmos")
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self.add_mod(self.pmos3)
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def setup_layout_constants(self):
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""" setup layout constraints """
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self.well_width = self.nmos1.active_position[0] \
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+ 3 * self.pmos1.active_width + drc["active_to_body_active"] \
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+ drc["well_enclosure_active"] - self.nmos3.active_contact.width \
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+ self.pmos1.active_contact.height + drc["minwidth_metal1"] \
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+ (drc["metal1_to_metal1"] - drc["well_enclosure_active"])
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self.width = self.width = self.well_width
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def add_rails(self):
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""" Add VDD and GND rails """
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rail_width = self.width
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self.rail_height = rail_height = drc["minwidth_metal1"]
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# Relocate the origin
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self.gnd_position = vector(0 , - 0.5 * drc["minwidth_metal1"])
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=self.gnd_position,
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width=rail_width,
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height=rail_height)
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self.vdd_position = vector(0, self.height - 0.5 * drc["minwidth_metal1"])
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=self.vdd_position,
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width=rail_width,
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height=rail_height)
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def add_ptx(self):
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""" transistors are added and placed inside the layout """
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# determines the spacing between the edge and nmos (rail to active
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# metal or poly_to_poly spacing)
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self.edge_to_nmos = max(drc["metal1_to_metal1"]
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- self.nmos1.active_contact_positions[0].y,
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0.5 * drc["poly_to_poly"] - 0.5 * drc["minwidth_metal1"]
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- self.nmos1.poly_positions[0].y)
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# Extra offset is calculated to make room for B and C contancts
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xoffset = (self.nmos1.active_contact.width
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+ drc["minwidth_metal1"]
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+ (drc["metal1_to_metal1"] - drc["well_enclosure_active"]))
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# determine the position of the first transistor from the left
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self.nmos_position1 = vector(xoffset,
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0.5 * drc["minwidth_metal1"] + self.edge_to_nmos)
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offset = self.nmos_position1 + vector(0,self.nmos1.height)
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self.add_inst(name="nmos1",
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mod=self.nmos1,
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offset=offset,
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mirror="MX")
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self.connect_inst(["net2", "A", "gnd", "gnd"])
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self.nmos_position2 = (self.nmos_position1
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+ vector(self.nmos2.active_width,0)
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- vector(self.nmos2.active_contact.width,0))
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offset = self.nmos_position2 + vector(0, self.nmos2.height)
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self.add_inst(name="nmos2",
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mod=self.nmos2,
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offset=offset,
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mirror="MX")
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self.connect_inst(["net1", "B", "net2", "gnd"])
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p2tp3 = vector(self.nmos3.active_width - self.nmos3.active_contact.width,
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self.nmos3.height)
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self.nmos_position3 = self.nmos_position2 + p2tp3
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self.add_inst(name="nmos3",
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mod=self.nmos3,
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offset=self.nmos_position3,
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mirror="MX")
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self.connect_inst(["Z", "C", "net1", "gnd"])
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# determines the spacing between the edge and pmos
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self.edge_to_pmos = max(drc["metal1_to_metal1"]
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- self.pmos1.active_contact_positions[0][1],
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0.5 * drc["poly_to_poly"] - 0.5 * drc["minwidth_metal1"]
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- self.pmos1.poly_positions[0][1])
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self.pmos_position1 = vector(self.nmos_position1[0],
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self.height - 0.5 * drc["minwidth_metal1"]
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- self.pmos1.height - self.edge_to_pmos)
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self.add_inst(name="pmos1",
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mod=self.pmos1,
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offset=self.pmos_position1)
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self.connect_inst(["Z", "A", "vdd", "vdd"])
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self.pmos_position2 = vector(self.nmos_position2.x, self.pmos_position1.y)
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self.add_inst(name="pmos2",
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mod=self.pmos2,
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offset=self.pmos_position2)
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self.connect_inst(["vdd", "B", "Z", "vdd"])
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self.pmos_position3 = vector(self.nmos_position3.x, self.pmos_position1.y)
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self.add_inst(name="pmos3",
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mod=self.pmos3,
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offset=self.pmos_position3)
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self.connect_inst(["Z", "C", "vdd", "vdd"])
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def add_well_contacts(self):
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""" create well contacts """
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layer_stack = ("active", "contact", "metal1")
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xoffset = (self.nmos_position3.x + self.pmos1.active_position.x
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+ self.pmos1.active_width + drc["active_to_body_active"])
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yoffset = self.pmos_position1.y + self.pmos1.active_contact_positions[0].y
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self.nwell_contact_position = vector(xoffset, yoffset)
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self.nwell_contact=self.add_contact(layer_stack,self.nwell_contact_position,(1,self.pmos1.num_of_tacts))
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xoffset = self.nmos_position3.x + (self.nmos1.active_position.x
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+ self.nmos1.active_width
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+ drc["active_to_body_active"])
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yoffset = self.nmos_position1.y + (self.nmos1.height
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- self.nmos1.active_contact_positions[0].y
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- self.nmos1.active_contact.height)
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self.pwell_contact_position = vector(xoffset, yoffset)
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self.pwell_contact=self.add_contact(layer_stack,self.pwell_contact_position,(1,self.nmos1.num_of_tacts))
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def connect_well_contacts(self):
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""" Connect well contacts to vdd and gnd rail """
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well_tap_length = self.height - self.nwell_contact_position[1]
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xoffset = (self.nwell_contact_position[0]
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+ self.nwell_contact.second_layer_position[0]
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- self.nwell_contact.first_layer_position[0])
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offset = [xoffset, self.nwell_contact_position.y]
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self.add_rect(layer="metal1",
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offset=offset,
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width=drc["minwidth_metal1"],
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height=well_tap_length)
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well_tap_length = self.nmos1.active_height
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offset = vector(self.pwell_contact_position
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+ self.pwell_contact.second_layer_position
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- self.pwell_contact.first_layer_position).scale(1,0)
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self.add_rect(layer="metal1",
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offset=offset,
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width=drc["minwidth_metal1"],
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height=well_tap_length)
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def connect_rails(self):
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""" Connect transistor pmos drains to vdd and nmos drains to gnd rail """
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correct = vector(self.pmos1.active_contact.width - drc["minwidth_metal1"],
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0).scale(0.5,0)
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poffset = self.pmos_position1 + self.pmos1.active_contact_positions[0] + correct
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temp_height = self.height - poffset[1]
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self.add_rect(layer="metal1",
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offset=poffset,
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width=drc["minwidth_metal1"],
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height=temp_height)
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poffset = [self.pmos_position3.x + self.pmos3.active_contact_positions[0].x + correct.x,
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poffset[1]]
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self.add_rect(layer="metal1",
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offset=poffset,
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width=drc["minwidth_metal1"],
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height=temp_height)
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poffset = self.nmos_position1 + self.nmos1.active_contact_positions[0] + correct
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self.add_rect(layer="metal1",
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offset=poffset.scale(1,0),
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width=drc["minwidth_metal1"],
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height=temp_height)
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def connect_tx(self):
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""" poly and drain connections """
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self.connect_poly()
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self.connect_drains()
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def connect_poly(self):
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""" Connect poly """
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yoffset_nmos1 = (self.nmos_position1.y + self.nmos1.poly_positions[0].y
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+ self.nmos1.poly_height)
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poly_length = (self.pmos_position1.y + self.pmos1.poly_positions[0].y
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- yoffset_nmos1 + drc["minwidth_poly"])
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offset = [self.nmos_position1[0] + self.nmos1.poly_positions[0][0],
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yoffset_nmos1 - drc["minwidth_poly"]]
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self.add_rect(layer="poly",
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offset=offset,
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width=drc["minwidth_poly"],
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height=poly_length)
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self.add_rect(layer="poly",
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offset=[offset[0] + self.pmos1.active_contact.width + 2 * drc["minwidth_poly"],
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offset[1]],
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width=drc["minwidth_poly"],
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height=poly_length)
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self.add_rect(layer="poly",
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offset=[offset[0] + 2 * self.pmos1.active_contact.width + 4 * drc["minwidth_poly"],
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offset[1]],
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width=drc["minwidth_poly"],
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height=poly_length)
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def connect_drains(self):
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""" Connect pmos and nmos drains. The output will be routed to this connection point. """
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yoffset = drc["minwidth_metal1"] + (self.nmos1.active_contact_positions[0].y
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- drc["well_enclosure_active"]
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+ drc["metal1_to_metal1"])
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drain_length = (self.height - yoffset + 0.5 * drc["minwidth_metal1"]
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- (self.pmos1.height - self.pmos1.active_contact_positions[0][1]))
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layer_stack = ("metal1", "via1", "metal2")
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for position in self.pmos1.active_contact_positions[1:][::2]:
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diff_active_via = self.pmos2.active_contact.width - self.m1m2_via.second_layer_width
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offset = (self.pmos_position2 + self.pmos2.active_contact_positions[0]
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+ vector(diff_active_via / 2,0))
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self.add_via(layer_stack,offset)
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width = (2 * self.pmos3.active_width
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- self.pmos3.active_contact.width
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- (self.pmos2.active_contact.width
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- self.m1m2_via.second_layer_width))
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self.add_rect(layer="metal2",
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offset=offset,
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width=width,
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height=self.m1m2_via.second_layer_width)
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xoffset = (self.pmos_position3.x + self.pmos3.active_contact_positions[1].x
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+ diff_active_via / 2)
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self.add_via(layer_stack,[xoffset,offset.y])
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xoffset = (self.nmos_position3[0] + self.nmos3.active_position[0]
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+ self.nmos3.active_width - self.nmos3.active_contact.width / 2)
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self.drain_position = vector(xoffset,
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drc["minwidth_metal1"] + drc["metal1_to_metal1"])
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length = self.height - 2 * (drc["minwidth_metal1"] + drc["metal1_to_metal1"])
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self.add_rect(layer="metal1",
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offset=self.drain_position,
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width=drc["minwidth_metal1"],
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height=length)
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def route_pins(self):
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""" input anbd output routing """
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self.route_input_gate_A()
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self.route_input_gate_B()
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self.route_input_gate_C()
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self.route_output()
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def route_input_gate_A(self):
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""" routing for input A """
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offset = (self.pmos_position1
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+ self.pmos1.poly_positions[0]
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- vector(drc["minwidth_poly"] / 2, self.poly_contact.width))
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self.add_contact(layers=("poly", "contact", "metal1"),
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offset=offset,
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rotate=90)
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self.add_rect(layer="poly",
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offset=offset + vector(drc["minwidth_poly"] / 2,0),
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width=-(self.poly_contact.first_layer_position[1] + drc["minwidth_poly"]),
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height=self.poly_contact.first_layer_width)
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offset = vector(offset.x,
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self.pmos_position1[1] + self.pmos1.poly_positions[0][1])
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self.add_layout_pin(text="A",
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layer="metal1",
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offset=offset,
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width=-offset.x,
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height=-drc["minwidth_metal1"])
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self.A_position = vector(0, offset.y - drc["minwidth_metal1"])
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def route_input_gate_B(self):
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""" routing for input B """
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xoffset = self.pmos2.poly_positions[0][0] \
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+ self.pmos_position2[0] - drc["minwidth_poly"]
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yoffset = self.nmos_position1[1] + self.nmos1.height \
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- drc["well_enclosure_active"] + (self.nmos1.active_contact.height \
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- self.nmos1.active_height) / 2 \
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+ drc["metal1_to_metal1"]
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self.add_contact(layers=("poly", "contact", "metal1"),
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offset=[xoffset,yoffset])
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=[xoffset,yoffset])
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xoffset = self.pmos2.poly_positions[0][0] + self.pmos_position2[0] \
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- drc["minwidth_poly"] + self.m1m2_via.width
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length = -xoffset + self.m1m2_via.width
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self.add_rect(layer="metal2",
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offset=[xoffset, yoffset],
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width=length,
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height=-drc["minwidth_metal2"])
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self.B_position = vector(0, yoffset - drc["minwidth_metal1"])
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self.add_label(text="B",
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layer="metal1",
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offset=self.B_position)
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xoffset = self.pmos_position1[0] + self.pmos1.active_position[0] \
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- drc["metal1_to_metal1"] + (self.pmos1.active_contact.width \
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- self.m1m2_via.second_layer_width) / 2
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=[xoffset,yoffset - drc["minwidth_metal2"]],
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rotate=90)
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self.add_rect(layer="metal1",
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offset=[xoffset, yoffset],
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width=-xoffset,
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height=-drc["minwidth_metal1"])
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def route_input_gate_C(self):
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""" routing for input A """
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xoffset = self.pmos3.poly_positions[0][0] \
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+ self.pmos_position3[0] - drc["minwidth_poly"]
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yoffset = self.nmos_position1[1] + self.nmos1.height \
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- drc["well_enclosure_active"] + (self.nmos1.active_contact.height \
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- self.nmos1.active_height) / 2 + drc["metal1_to_metal1"]
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self.add_contact(layers=("poly", "contact", "metal1"),
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offset=[xoffset,yoffset])
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self.add_via(layers=("metal1", "via1", "metal2"),
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offset=[xoffset,yoffset])
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xoffset = self.pmos3.poly_positions[0][0] \
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+ self.pmos_position3[0] - drc["minwidth_poly"] \
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+ self.m1m2_via.width
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length = -xoffset + self.m1m2_via.width
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self.add_rect(layer="metal2",
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offset=[xoffset,
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yoffset - drc["minwidth_metal2"] - drc["metal2_to_metal2"]],
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width=length,
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height=-drc["minwidth_metal2"])
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# FIXME: Convert to add_layout_pin?
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self.add_rect(layer="metal2",
|
|
offset=[xoffset - self.m1m2_via.width,
|
|
yoffset],
|
|
width=self.m1m2_via.width,
|
|
height=-drc["minwidth_metal2"] - drc["metal2_to_metal2"])
|
|
self.C_position = vector(0,
|
|
self.B_position[1] - drc["metal2_to_metal2"] - drc["minwidth_metal1"] \
|
|
- (self.m1m2_via.second_layer_width
|
|
- self.m1m2_via.first_layer_width))
|
|
self.add_label(text="C",
|
|
layer="metal1",
|
|
offset=self.C_position)
|
|
|
|
xoffset = self.pmos_position1[0] + self.pmos1.active_position[0] \
|
|
- drc["metal1_to_metal1"] + (self.pmos1.active_contact.width \
|
|
- self.m1m2_via.second_layer_width) / 2
|
|
self.add_via(layers=("metal1", "via1", "metal2"),
|
|
offset=[xoffset,
|
|
yoffset - 2 * drc["minwidth_metal2"] - self.m1m2_via.width],
|
|
rotate=90)
|
|
self.add_rect(layer="metal1",
|
|
offset=[xoffset,
|
|
yoffset - 2 * drc["minwidth_metal2"]],
|
|
width=-xoffset,
|
|
height=-drc["minwidth_metal1"])
|
|
|
|
def route_output(self):
|
|
""" routing for output Z """
|
|
xoffset = self.nmos_position3[0] + self.nmos3.active_position[0] \
|
|
+ self.nmos3.active_width - self.nmos3.active_contact.width / 2
|
|
yoffset = (self.nmos1.height + (self.height - drc["minwidth_metal1"]
|
|
- self.pmos1.height - self.nmos1.height) / 2
|
|
- (drc["minwidth_metal1"] / 2))
|
|
# FIXME Convert to add_layout_pin?
|
|
self.add_rect(layer="metal1",
|
|
offset=[xoffset, yoffset],
|
|
width=self.well_width - xoffset,
|
|
height=drc["minwidth_metal1"])
|
|
|
|
self.Z_position = vector(self.well_width, yoffset)
|
|
self.add_label(text="Z",
|
|
layer="metal1",
|
|
offset=self.Z_position)
|
|
|
|
def extend_wells(self):
|
|
""" extension of well """
|
|
middle_point = self.nmos_position1[1] + self.nmos1.pwell_position[1] \
|
|
+ self.nmos1.well_height + (self.pmos_position1[1]
|
|
+ self.pmos1.nwell_position[1]
|
|
- self.nmos_position1[1]
|
|
- self.nmos1.pwell_position[1]
|
|
- self.nmos1.well_height) / 2
|
|
offset = self.nwell_position = vector(0, middle_point)
|
|
self.nwell_height = self.height - middle_point
|
|
self.add_rect(layer="nwell",
|
|
offset=offset,
|
|
width=self.well_width,
|
|
height=self.nwell_height)
|
|
self.add_rect(layer="vtg",
|
|
offset=offset,
|
|
width=self.well_width,
|
|
height=self.nwell_height)
|
|
|
|
offset = self.pwell_position = vector(0, 0)
|
|
self.pwell_height = middle_point
|
|
self.add_rect(layer="pwell",
|
|
offset=offset, width=self.well_width,
|
|
height=self.pwell_height)
|
|
self.add_rect(layer="vtg",
|
|
offset=offset,
|
|
width=self.well_width,
|
|
height=self.pwell_height)
|
|
|
|
def extend_active(self):
|
|
""" extension of active region """
|
|
self.active_width = self.pmos1.active_width \
|
|
+ drc["active_to_body_active"] + self.pmos1.active_contact.width
|
|
offset = (self.pmos1.active_position+self.pmos_position3.scale(1,0)
|
|
+ self.pmos_position1.scale(0,1))
|
|
self.add_rect(layer="active",
|
|
offset=offset,
|
|
width=self.active_width,
|
|
height=self.pmos1.active_height)
|
|
|
|
offset = offset + vector(self.pmos1.active_width,0)
|
|
width = self.active_width - self.pmos1.active_width
|
|
self.add_rect(layer="nimplant",
|
|
offset=offset,
|
|
width=width,
|
|
height=self.pmos1.active_height)
|
|
|
|
offset = [self.nmos_position3[0] + self.nmos1.active_position[0],
|
|
self.nmos_position1[1] + self.nmos1.height
|
|
- self.nmos1.active_position[1] - self.nmos1.active_height]
|
|
self.add_rect(layer="active",
|
|
offset=offset,
|
|
width=self.active_width,
|
|
height=self.nmos1.active_height)
|
|
|
|
offset = offset + vector(self.nmos1.active_width,0)
|
|
width = self.active_width - self.nmos1.active_width
|
|
self.add_rect(layer="pimplant",
|
|
offset=offset,
|
|
width=width,
|
|
height=self.nmos1.active_height)
|
|
|
|
def setup_layout_offsets(self):
|
|
""" Defining the position of i/o pins for the three input nand gate """
|
|
self.A_position = self.A_position
|
|
self.B_position = self.B_position
|
|
self.C_position = self.C_position
|
|
self.Z_position = self.Z_position
|
|
self.vdd_position = self.vdd_position
|
|
self.gnd_position = self.gnd_position
|