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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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7fc4469b97794c1489a280367affb4865c69cd20
OpenRAM/technology/scn4m_subm
T
History
Hunter Nichols 10085d85ab Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.
2021-07-21 14:59:02 -07:00
..
gds_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
mag_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
models
Adjusted vth0 of FF and SS models in scn4m from nominal.
2019-10-07 15:26:20 -07:00
sim_data
Added more data for regression modules.
2021-06-21 17:21:00 -07:00
sp_lib
Rework bitcells.
2020-11-13 10:07:40 -08:00
tech
Changed CACTI drain cap function to be roughly equivalent but use less parameters. Added drain cap functions to relevant modules. Added drain cap parameters in tech files.
2021-07-21 14:59:02 -07:00
tf
Add draft lyt file -- connectivity not working
2020-08-14 10:38:22 -07:00
__init__.py
update copyright year.
2021-01-22 11:24:53 -08:00
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