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luke
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OpenRAM
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7ce75398a8e4f3fc6178441eb55be65a99429d7f
OpenRAM
/
compiler
/
pgates
T
History
Matt Guthaus
2ed8fc1506
pgate inputs and outputs are all on M1 for flexible via placement when using gates.
2018-11-28 12:42:29 -08:00
..
pand2.py
pgate inputs and outputs are all on M1 for flexible via placement when using gates.
2018-11-28 12:42:29 -08:00
pbuf.py
pgate inputs and outputs are all on M1 for flexible via placement when using gates.
2018-11-28 12:42:29 -08:00
pgate.py
…
pinv.py
…
pinvbuf.py
…
pnand2.py
Add netlist only mode to new pgates
2018-11-26 15:29:42 -08:00
pnand3.py
…
pnor2.py
…
precharge.py
Change en to en_bar in precharge. Fix logic for inverted p_en_bar.
2018-11-27 14:17:55 -08:00
ptx.py
Limit ps, pd, as, ad precision in ptx.
2018-11-28 09:47:54 -08:00
single_level_column_mux.py
…