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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
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7b4e00188573e2a30f1f1e6d36e0d20d3c81aa3c
OpenRAM/compiler/characterizer
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Hunter Nichols 7b4e001885 Altered web to only be generated for rw ports.
2018-10-04 15:08:12 -07:00
..
__init__.py
Adding simulation.py for common functions between functional and delay tests. Updating functional test.
2018-10-04 09:29:44 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Altered web to only be generated for rw ports.
2018-10-04 15:08:12 -07:00
functional.py
Correcting functional inheritance from simulation.
2018-10-04 13:55:59 -07:00
lib.py
Fixed bugs to allow characterization of multiple read ports. Improved some debug messages.
2018-10-04 14:09:09 -07:00
setup_hold.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
simulation.py
Adding simulation.py for common functions between functional and delay tests. Updating functional test.
2018-10-04 09:29:44 -07:00
stimuli.py
Altered web to only be generated for rw ports.
2018-10-04 15:08:12 -07:00
trim_spice.py
Fixed bugs in power simulations. Made regex raw strings to remove warnings
2018-10-04 14:09:09 -07:00
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