Jesse Cirimelli-Low 781bd13cc1 Merge branch 'dev' into datasheet_gen

2018-11-07 10:08:45 -08:00

..

base

Merge branch 'dev' into datasheet_gen

2018-11-07 10:08:45 -08:00

bitcells

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00

characterizer

Merge branch 'dev' into datasheet_gen

2018-11-07 10:08:45 -08:00

datasheet

added DRC/LVS error count to datasheet

2018-11-01 14:02:33 -07:00

drc

Moving wide metal spacing to routing grid level

2018-10-15 09:59:16 -07:00

gdsMill

Allow multiple must-connect pins with the same label.

2018-11-07 13:05:13 -08:00

modules

Reimplement gdsMill pin functions so they are run once when a GDS is loaded. Get pins is now a table lookup.

2018-11-07 11:31:44 -08:00

pgates

Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell.

2018-10-18 07:05:47 -07:00

router

Allow multiple must-connect pins with the same label.

2018-11-07 13:05:13 -08:00

tests

Merge branch 'dev' into datasheet_gen

2018-11-07 10:08:45 -08:00

verify

Remove redundant DRC run in magic.

2018-11-05 13:30:42 -08:00

debug.py

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example_config_freepdk45.py

Remove options from example config files

2018-11-05 12:47:47 -08:00

example_config_scn4m_subm.py

Remove options from example config files

2018-11-05 12:47:47 -08:00

gen_stimulus.py

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globals.py

added config file to datasheet and output files

2018-10-31 12:29:13 -07:00

Makefile

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openram.py

added config file to datasheet and output files

2018-10-31 12:29:13 -07:00

options.py

Fix openram_temp directory

2018-10-06 08:08:01 -07:00

sram_1bank.py

Merge branch 'multiport' into supply_routing

2018-10-11 09:56:38 -07:00

sram_2bank.py

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sram_4bank.py

Converted all submodules to use _bit notation instead of [bit]

2018-10-11 09:53:08 -07:00

sram_base.py

Altered bitline with heuristic to have a larger delay chain for larger column muxes. Also have to alter the feasible period for functional tests to pass.

2018-10-30 22:19:26 -07:00

sram_config.py

Added custom 1rw+1r bitcell. Testing are currently failing.

2018-10-22 17:02:21 -07:00

sram.py

added config file to datasheet and output files

2018-10-31 12:29:13 -07:00