OpenRAM/compiler/verify
Michael Timothy Grimes e118cc2d5c Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-29 16:06:50 -07:00
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__init__.py Add parameters to give preference to DRC/LVS/PEX tools like we do for spice. 2018-08-28 13:41:26 -07:00
assura.py Add DRC/LVS/PEX statistics in verbose=1 mode 2018-07-11 11:59:24 -07:00
calibre.py Add temporary options to LVS to allow name merging 2018-07-18 15:10:29 -07:00
magic.py Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport 2018-08-29 16:06:50 -07:00