Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
75da5a994b6fed44e7bf01cb9153a69875143ea4
OpenRAM/compiler/characterizer
T
History
Hunter Nichols 75da5a994b Edited create_test_cycles to generate values that characterize all ports. Still several bugs and lib file does not support multiple ports.
2018-08-28 00:30:15 -07:00
..
__init__.py
Fix option reload problems and checkpointing so that it works properly.
2018-07-11 12:00:15 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Edited create_test_cycles to generate values that characterize all ports. Still several bugs and lib file does not support multiple ports.
2018-08-28 00:30:15 -07:00
lib.py
Fixed timing to be measured from positive clock edge since
2018-07-26 13:58:50 -07:00
setup_hold.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
stimuli.py
Added basic structure to add_test_cycles to characterize multiple ports and its helper functions to allow for ports to be selected for characterization
2018-08-27 15:56:42 -07:00
trim_spice.py
Convert bitline index to integer in trim_spice
2018-07-26 14:29:44 -07:00
Powered by Gitea Version: 1.27.2 Page: 274ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API