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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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6efe0f56c2e2dbfce72130119d597235757faa39
OpenRAM/compiler/characterizer
T
History
Hunter Nichols 8e243258e4 Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell.
2018-10-26 00:08:12 -07:00
..
__init__.py
Fix check for missing simulator type in characterizer
2018-10-25 09:08:56 -07:00
charutils.py
Fix module import names for python3. Rename parse function to something meaningful.
2018-06-29 09:45:07 -07:00
delay.py
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
functional.py
Altering comment code in simulation.py to match the needs of delay.py
2018-10-25 00:58:01 -07:00
lib.py
Added updated 1rw 1r bitcell with a text boundary. Added bitcell array test for the bitcell.
2018-10-26 00:08:12 -07:00
setup_hold.py
Updating ms_flop removal.
2018-09-13 11:40:24 -07:00
simulation.py
Altering comment code in simulation.py to match the needs of delay.py
2018-10-25 00:58:01 -07:00
stimuli.py
Add ngspice equivalents of RUNLVL
2018-10-24 10:31:27 -07:00
trim_spice.py
Fixed merge conflicts with sram.py
2018-10-22 17:29:14 -07:00
worst_case.py
Made delay.py a child of simulation.py. Removed duplicate code in delay and changed some in simulation
2018-10-09 17:44:28 -07:00
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