OpenRAM/compiler/tests at 6e90bf0d6d0dccd2c1f70544796fd18dbe3277d7 - OpenRAM - Gitea: Git with a cup of tea

luke/OpenRAM

mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 18:02:23 +02:00

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mguthaus 6e90bf0d6d Enable output filename and path to be in config file. Command line will over-ride config file.

2017-06-12 14:37:15 -07:00

..

New lib file. Tolerances were off.

2017-06-06 11:06:16 -07:00

00_code_format_check_test.py

Fixed format errors

2017-04-24 13:50:19 -07:00

01_library_drc_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

02_library_lvs_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

03_contact_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

03_path_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

03_ptx_1finger_nmos_test.py

Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules.

2017-04-26 14:33:03 -07:00

03_ptx_1finger_pmos_test.py

Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules.

2017-04-26 14:33:03 -07:00

03_ptx_3finger_nmos_test.py

Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules.

2017-04-26 14:33:03 -07:00

03_ptx_3finger_pmos_test.py

Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules.

2017-04-26 14:33:03 -07:00

03_wire_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

04_nand_2_test.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

04_nand_3_test.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

04_nor_2_test.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

04_pinv_test.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

04_wordline_driver_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

05_bitcell_array_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

06_hierarchical_decoder_test.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

06_hierarchical_predecode2x4_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

06_hierarchical_predecode3x8_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

07_single_level_column_mux_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

08_precharge_array_test.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

09_sense_amp_array_test.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

10_write_driver_array_test.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

11_ms_flop_array_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

13_control_logic_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

14_logic_effort_dc_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

15_tri_gate_array_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

16_replica_bitline_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

19_bank_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

20_sram_1bank_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

20_sram_2bank_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

20_sram_4bank_test.py

Merge use-temp-dir-pid

2016-11-12 08:55:42 -08:00

21_hspice_delay_test.py

run_pex argument is now use_pex. Each unit test must RESET its options before assertions for consistent start state.

2016-11-15 09:03:16 -08:00

21_hspice_hold_test.py

run_pex argument is now use_pex. Each unit test must RESET its options before assertions for consistent start state.

2016-11-15 09:03:16 -08:00

21_hspice_setup_test.py

run_pex argument is now use_pex. Each unit test must RESET its options before assertions for consistent start state.

2016-11-15 09:03:16 -08:00

21_ngspice_delay_test.py

Fix ngspice scnmos results

2016-11-15 10:13:45 -08:00

21_ngspice_hold_test.py

run_pex argument is now use_pex. Each unit test must RESET its options before assertions for consistent start state.

2016-11-15 09:03:16 -08:00

21_ngspice_setup_test.py

run_pex argument is now use_pex. Each unit test must RESET its options before assertions for consistent start state.

2016-11-15 09:03:16 -08:00

22_pex_func_test_with_pinv.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

22_sram_func_test.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

23_lib_sram_model_test.py

Fix lib test to enable spice simulation. Fixed bug with change in default argument.

2017-06-05 09:07:52 -07:00

23_lib_sram_test.py

Fix lib test to enable spice simulation. Fixed bug with change in default argument.

2017-06-05 09:07:52 -07:00

24_lef_sram_test.py

Moved output of tests 23-25 to openram_temp

2016-11-12 11:15:34 -08:00

25_verilog_sram_test.py

Moved output of tests 23-25 to openram_temp

2016-11-12 11:15:34 -08:00

30_openram_test.py

Moved output of tests 30 to openram_temp

2016-11-12 11:15:55 -08:00

config_20_freepdk45.py

Enable output filename and path to be in config file. Command line will over-ride config file.

2017-06-12 14:37:15 -07:00

config_20_scn3me_subm.py

Enable output filename and path to be in config file. Command line will over-ride config file.

2017-06-12 14:37:15 -07:00

README

RELEASE 1.0

2016-11-08 09:57:35 -08:00

regress.py

Change some debug levels. Fix ngspice test values. ix cwd warning in some tests.

2016-11-15 08:57:06 -08:00

sram_tb.v

RELEASE 1.0

2016-11-08 09:57:35 -08:00

testutils.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

README

Note that the tests turn off DRC/LVS when they perform their own check
for performance improvement. However, it must be turned back on before
the test runs an assert.