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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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6cde6beafa86f53ee64df4568679bb46f5d4924e
OpenRAM/technology/freepdk45/gds_lib
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Hunter Nichols 1e87a0efd2 Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
..
cell_1rw_1r.gds
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
cell_6t.gds
Remove layer 230 labels from library cells
2018-11-09 11:08:20 -08:00
dff.gds
Add dff_buf and dff_array modules.
2018-03-23 08:11:51 -07:00
replica_cell_1rw_1r.gds
Re-added new width 1rw,1r bitcells with flattened gds.
2018-12-05 20:43:10 -08:00
replica_cell_6t.gds
Remove layer 230 labels from library cells
2018-11-09 11:12:31 -08:00
sense_amp.gds
Remove layer 230 labels from library cells
2018-11-09 11:02:19 -08:00
tri_gate.gds
Move sense amp to tri gate routing to M3... not ideal.
2018-04-23 09:14:18 -07:00
write_driver.gds
Remove layer 230 labels from library cells
2018-11-09 11:02:19 -08:00
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