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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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6cdc870091d07f3e6bd633837087684968f2f678
OpenRAM/compiler/characterizer
T
History
Matt Guthaus 583dc4410b Revert bus bits back into pins
2019-02-22 16:22:27 -08:00
..
__init__.py
Merge branch 'dev' into multiport_characterization
2019-01-15 16:33:39 -08:00
bitline_delay.py
Added slews measurements to the model checker. Removed unused code in bitline delay class.
2019-01-09 22:42:34 -08:00
charutils.py
Added data parsing to measurement objects and adding power measurements.
2018-12-20 15:54:56 -08:00
delay.py
Fix bitline measurement delays and adjusted default delay chain for column mux srams
2019-02-06 00:46:25 -08:00
functional.py
…
lib.py
Revert bus bits back into pins
2019-02-22 16:22:27 -08:00
logical_effort.py
Moved all bitline delay measurements to delay class. Added measurements to check delay model.
2019-01-03 05:51:28 -08:00
measurements.py
Fix bitline measurement delays and adjusted default delay chain for column mux srams
2019-02-06 00:46:25 -08:00
model_check.py
Added more variance analysis for the delay data
2019-02-07 02:27:22 -08:00
setup_hold.py
…
simulation.py
…
stimuli.py
Added bitline measures with hardcoded names.
2018-12-12 00:43:08 -08:00
trim_spice.py
Added bitline measures with hardcoded names.
2018-12-12 00:43:08 -08:00
worst_case.py
…
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