mirror of https://github.com/VLSIDA/OpenRAM.git
6c7c6a9fba
The `wire_spice_model()` expects `spice["wire_unit_c"]` in Farads per micrometer squared (F/um²). This is given correctly in the FreePDK45 tech but incorrectly in other technologies. This leads to a huge overestimation of wire capacitance in those technologies, leading to incorrect power values. |
||
|---|---|---|
| .. | ||
| __init__.py | ||
| channel_route.py | ||
| contact.py | ||
| delay_data.py | ||
| design.py | ||
| errors.py | ||
| geometry.py | ||
| hierarchy_design.py | ||
| hierarchy_layout.py | ||
| hierarchy_spice.py | ||
| lef.py | ||
| logical_effort.py | ||
| pin_layout.py | ||
| power_data.py | ||
| rom_verilog.py | ||
| route.py | ||
| timing_graph.py | ||
| utils.py | ||
| vector.py | ||
| vector3d.py | ||
| verilog.py | ||
| wire.py | ||
| wire_path.py | ||
| wire_spice_model.py | ||