mirror of https://github.com/VLSIDA/OpenRAM.git
6c7c6a9fba
The `wire_spice_model()` expects `spice["wire_unit_c"]` in Farads per micrometer squared (F/um²). This is given correctly in the FreePDK45 tech but incorrectly in other technologies. This leads to a huge overestimation of wire capacitance in those technologies, leading to incorrect power values. |
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| .. | ||
| base | ||
| characterizer | ||
| datasheet | ||
| drc | ||
| gdsMill | ||
| model_configs | ||
| modules | ||
| router | ||
| tests | ||
| verify | ||
| Makefile | ||
| debug.py | ||
| gen_stimulus.py | ||
| globals.py | ||
| model_data_util.py | ||
| options.py | ||
| rom.py | ||
| rom_config.py | ||
| run_profile.sh | ||
| sram.py | ||
| sram_config.py | ||
| sram_factory.py | ||
| view_profile.py | ||