mirror of https://github.com/VLSIDA/OpenRAM.git
121 lines
3.7 KiB
Markdown
121 lines
3.7 KiB
Markdown
# OpenRAM Documentation
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These pages provide the documentation of OpenRAM. You can use the links below to
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navigate through the documentation.
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## Table of Contents
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1. [OpenRAM Dependencies](#openram-dependencies)
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1. [Supported Technologies](#supported-technologies)
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1. [Online Playground](./OpenRAM.ipynb)
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1. [Basic Setup](./basic_setup.md#go-back)
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1. [Basic SRAM Usage](./basic_usage.md#go-back)
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1. [Basic ROM Usage](./basic_rom_usage.md#go-back)
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1. [Python Library](./python_library.md#go-back)
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1. [Bitcells](./bitcells.md#go-back)
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1. [Architecture](./architecture.md#go-back)
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1. [Implementation](#implementation)
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1. [Technology and Tool Portability](#technology-and-tool-portability)
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1. [Tutorials](./tutorials.md#go-back)
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1. [Debugging and Unit Testing](./debug.md#go-back)
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1. [Technology Setup](./technology_setup.md#go-back)
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1. [Library Cells](./library_cells.md#go-back)
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1. [Base Data Structures](./base_data_structures.md#go-back)
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1. [Hierarchical Design Modules](./design_modules.md#go-back)
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1. [Control Logic and Timing](./control_logic.md#go-back)
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1. [Routing](./routing.md#go-back)
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1. [Characterization](./characterization.md#go-back)
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1. [Results](./results.md#go-back)
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1. [FAQ](./FAQ.md#go-back)
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1. [Contributors/Collaborators](#contributorscollaborators)
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## OpenRAM Dependencies
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In general, the OpenRAM compiler has very few dependencies:
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+ Git
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+ Make
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+ Python 3.5 or higher
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+ Various Python packages (pip install -r requirements.txt)
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+ Anaconda
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Commercial tools (optional):
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* Spice Simulator
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* Hspice I-2013.12-1 (or later)
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* CustomSim 2017 (or later)
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* DRC
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* Calibre 2017.3\_29.23
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* LVS
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* Calibre 2017.3\_29.23
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## Supported Technologies
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* NCSU FreePDK 45nm
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* Non-fabricable but contains DSM rules
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* Calibre or klayout for DRC/LVS
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* MOSIS 0.35um (SCN4M\_SUBM)
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* Fabricable technology
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* Magic/Netgen or Calibre for DRC/LVS
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* Skywater 130nm (sky130)
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* Fabricable technology
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* Magic/Netgen or klayout
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## Implementation
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* Front-end mode
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* Generates SPICE, layout views, timing models
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* Netlist-only mode can skip the physical design too
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* Doesn't perform DRC/LVS
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* Estimates power/delay analytically
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* Back-end mode
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* Generates SPICE, layout views, timing models
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* Performs DRC/LVS
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* Can perform at each level of hierarchy or at the end
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* Simulates power/delay
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* Can be back-annotated or not
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## Technology and Tool Portability
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* OpenRAM is technology independent by using a technology directory that
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includes:
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* Technology's specific information
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* Technology's rules such as DRC rules and the GDS layer map
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* Custom designed library cells (6T, sense amp, DFF) to improve the SRAM
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density.
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* For technologies that have specific design requirements, such as specialized
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well contacts, the user can include helper functions in the technology
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directory.
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* Verification wrapper scripts
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* Uses a wrapper interface with DRC and LVS tools that allow flexibility
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* DRC and LVS can be performed at all levels of the design hierarchy to
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enhance bug tracking.
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* DRC and LVS can be disabled completely for improved run-time or if
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licenses are not available.
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## Contributors/Collaborators
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<img align="right" height="120" src="../assets/images/logos/okstate.png">
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* Prof. Matthew Guthaus (UCSC)
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* Prof. James Stine & Dr. Samira Ataei (Oklahoma State University)
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* UCSC students:
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* Bin Wu
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* Hunter Nichols
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* Michael Grimes
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* Jennifer Sowash
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* Jesse Cirimelli-Low
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<img align="right" height="100" src="../assets/images/logos/vlsida.png">
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* Many other past students:
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* Jeff Butera
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* Tom Golubev
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* Marcelo Sero
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* Seokjoong Kim
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* Sage Walker
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