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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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67dbb4893eabc6818d30f6590bd3a079b0ec0f5b
OpenRAM
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technology
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scn4m_subm
T
History
Hunter Nichols
6efe0f56c2
Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
2018-10-26 00:08:13 -07:00
..
gds_lib
Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
2018-10-26 00:08:13 -07:00
mag_lib
Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
2018-10-26 00:08:13 -07:00
models
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
sp_lib
Added gds/sp for scn4m 1rw+1r bitcell. Passes DRC/LVS in both technologies for single and array.
2018-10-26 00:08:13 -07:00
sue_lib
Added scn4m_subm.
2018-09-13 12:53:35 -07:00
tech
Fixed spacing in golden lib files. Added column mux into analytical model.
2018-10-24 00:16:26 -07:00
tf
Supply router working except:
2018-09-18 12:57:39 -07:00
