mirror of https://github.com/VLSIDA/OpenRAM.git
219 lines
7.1 KiB
Markdown
219 lines
7.1 KiB
Markdown
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# OpenRAM
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[](https://www.python.org/)
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[](./LICENSE)
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[](https://github.com/VLSIDA/OpenRAM/archive/stable.zip)
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[](https://github.com/VLSIDA/OpenRAM/archive/dev.zip)
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An open-source static random access memory (SRAM) compiler.
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# What is OpenRAM?
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<img align="right" width="25%" src="images/SCMOS_16kb_sram.jpg">
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OpenRAM is an award winning open-source Python framework to create the layout,
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netlists, timing and power models, placement and routing models, and
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other views necessary to use SRAMs in ASIC design. OpenRAM supports
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integration in both commercial and open-source flows with both
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predictive and fabricable technologies.
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# Documentation
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Please take a look at our presentation We have created a detailed
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presentation that serves as our [documentation][documentation].
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This is the most up-to-date information, so please let us know if you see
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things that need to be fixed.
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# Basic Setup
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## Docker
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We have a [docker setup](./docker) to run OpenRAM.
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## Dependencies
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The OpenRAM compiler has very few dependencies:
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+ [Ngspice] 34 (or later) or HSpice I-2013.12-1 (or later) or CustomSim 2017 (or later) or [Xyce] 7.4 (or later)
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+ Python 3.6 or higher
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+ Various Python packages (pip install -r requirements.txt)
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+ [Git]
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If you want to perform DRC and LVS, you will need either:
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+ Calibre (for [FreePDK45])
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+ [Magic] 8.3.197 or newer
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+ [Netgen] 1.5.195 or newer
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You must set two environment variables:
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+ OPENRAM\_HOME should point to the compiler source directory.
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+ OPENERAM\_TECH should point to one or more root technology directories (colon separated).
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## Environment
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For example add this to your .bashrc:
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```
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export OPENRAM_HOME="$HOME/openram/compiler"
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export OPENRAM_TECH="$HOME/openram/technology"
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```
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You may also wish to add OPENRAM\_HOME to your PYTHONPATH:
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```
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export PYTHONPATH="$PYTHONPATH:$OPENRAM_HOME"
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We include the tech files necessary for [SCMOS] SCN4M_SUBM,
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[FreePDK45]. The [SCMOS] spice models, however, are
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generic and should be replaced with foundry models. You may get the
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entire [FreePDK45 PDK here][FreePDK45].
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```
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### Sky130 Setup
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To install [Sky130], you must have the open_pdks files installed in $PDK_ROOT.
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To install this automatically, you can run:
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cd $HOME/openram
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make pdk
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Then you must also install the [Sky130] SRAM build space and the appropriate cell views
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by running:
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cd $HOME/openram
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make install
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```
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# Basic Usage
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Once you have defined the environment, you can run OpenRAM from the command line
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using a single configuration file written in Python.
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For example, create a file called *myconfig.py* specifying the following
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parameters for your memory:
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# Data word size
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word_size = 2
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# Number of words in the memory
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num_words = 16
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# Technology to use in $OPENRAM_TECH
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tech_name = "scn4m_subm"
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# You can use the technology nominal corner only
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nominal_corner_only = True
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# Or you can specify particular corners
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# Process corners to characterize
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# process_corners = ["SS", "TT", "FF"]
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# Voltage corners to characterize
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# supply_voltages = [ 3.0, 3.3, 3.5 ]
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# Temperature corners to characterize
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# temperatures = [ 0, 25 100]
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# Output directory for the results
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output_path = "temp"
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# Output file base name
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output_name = "sram_{0}_{1}_{2}".format(word_size,num_words,tech_name)
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# Disable analytical models for full characterization (WARNING: slow!)
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# analytical_delay = False
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```
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You can then run OpenRAM by executing:
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```
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python3 $OPENRAM_HOME/openram.py myconfig
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```
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You can see all of the options for the configuration file in
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$OPENRAM\_HOME/options.py
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To run designs in Docker, it is suggested to use, for example:
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```
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cd openram/macros
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make example_config_scn4m_subm
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```
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# Unit Tests
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Regression testing performs a number of tests for all modules in OpenRAM.
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From the unit test directory ($OPENRAM\_HOME/tests),
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use the following command to run all regression tests:
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```
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cd openram/compiler/tests
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make -j 3
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```
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The -j can run with 3 threads. By default, this will run in all technologies.
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To run a specific test:
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```
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ce openram/compiler/tests
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make 05_bitcell_array_test
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To run a specific technology:
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cd openram/compiler/tests
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TECHS=scn4m_subm make 05_bitcell_array_test
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To increase the verbosity of the test, add one (or more) -v options and
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pass it as an argument to OpenRAM:
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```
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ARGS="-v" make 05_bitcell_array_test
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# Get Involved
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+ [Port it](./PORTING.md) to a new technology.
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+ Report bugs by submitting [Github issues].
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+ Develop new features (see [how to contribute](./CONTRIBUTING.md))
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+ Submit code/fixes using a [Github pull request]
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+ Follow our [project][Github project].
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+ Read and cite our [ICCAD paper][OpenRAMpaper]
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# Further Help
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+ [Additional hints](./HINTS.md)
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+ [Documentation][documentation]
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+ [OpenRAM Slack Workspace][Slack]
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+ [OpenRAM Users Group][user-group] ([subscribe here][user-group-subscribe])
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+ [OpenRAM Developers Group][dev-group] ([subscribe here][dev-group-subscribe])
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# License
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OpenRAM is licensed under the [BSD 3-clause License](./LICENSE).
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# Contributors & Acknowledgment
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- [Matthew Guthaus] from [VLSIDA] created the OpenRAM project and is the lead architect.
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- [James Stine] from [VLSIARCH] co-founded the project.
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- Many students: Hunter Nichols, Michael Grimes, Jennifer Sowash, Yusu Wang, Joey Kunzler, Jesse Cirimelli-Low, Samira Ataei, Bin Wu, Brian Chen, Jeff Butera
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If I forgot to add you, please let me know!
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* * *
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[Matthew Guthaus]: https://users.soe.ucsc.edu/~mrg
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[James Stine]: https://ece.okstate.edu/content/stine-james-e-jr-phd
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[VLSIDA]: https://vlsida.soe.ucsc.edu
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[VLSIARCH]: https://vlsiarch.ecen.okstate.edu/
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[OpenRAMpaper]: https://ieeexplore.ieee.org/document/7827670/
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[Github issues]: https://github.com/VLSIDA/OpenRAM/issues
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[Github pull request]: https://github.com/VLSIDA/OpenRAM/pulls
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[Github project]: https://github.com/VLSIDA/OpenRAM
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[documentation]: https://docs.google.com/presentation/d/10InGB33N51I6oBHnqpU7_w9DXlx-qe9zdrlco2Yc5co/edit?usp=sharing
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[dev-group]: mailto:openram-dev-group@ucsc.edu
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[user-group]: mailto:openram-user-group@ucsc.edu
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[dev-group-subscribe]: mailto:openram-dev-group+subscribe@ucsc.edu
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[user-group-subscribe]: mailto:openram-user-group+subscribe@ucsc.edu
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[Magic]: http://opencircuitdesign.com/magic/
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[Netgen]: http://opencircuitdesign.com/netgen/
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[Qflow]: http://opencircuitdesign.com/qflow/history.html
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[Ngspice]: http://ngspice.sourceforge.net/
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[Xyce]: http://xyce.sandia.gov/
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[Git]: https://git-scm.com/
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[FreePDK45]: https://www.eda.ncsu.edu/wiki/FreePDK45:Contents
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[SCMOS]: https://www.mosis.com/files/scmos/scmos.pdf
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[Sky130]: https://github.com/google/skywater-pdk-libs-sky130_fd_bd_sram.git
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[Slack]: https://join.slack.com/t/openram/shared_invite/enQtNDgxMjc3NzU5NTI1LWZiYWMwNjNkZThmYTdkODc3NDE1NDhjNzUxNDhmMDQ4ZTM3NDgwNWFlNjM5NWFiZDkyMzBlNzc1NTg3ZjllNTY
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