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base
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Clean up GdsMill. Fix rotate bug I introduced in transFlags!
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2018-08-29 15:34:45 -07:00 |
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characterizer
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Remove OEB signal since we split DIN/DOUT ports
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2018-08-13 14:09:49 -07:00 |
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gdsMill
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Revert all transFlags in GdsMill
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2018-08-29 17:23:04 -07:00 |
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modules
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Merging changes and updating multiport syntax across several tests
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2018-09-03 19:36:20 -07:00 |
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pgates
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Commiting changes to pbitcell that separate the routing into individual functions and rename. The bitlines and wordlines are also renamed.
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2018-09-06 17:59:21 -07:00 |
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router
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Merge branch 'supply_routing' of https://github.com/VLSIDA/PrivateRAM into supply_routing
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2018-08-29 15:40:04 -07:00 |
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tests
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Merging changes and updating multiport syntax across several tests
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2018-09-03 19:36:20 -07:00 |
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verify
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Use a .magicrc in the technology directory to read magic tech files
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2018-08-30 14:20:41 -07:00 |
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Makefile
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Add Makefile for parallel test execution.
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2018-01-22 13:39:07 -08:00 |
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debug.py
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Output debug warnings and errors to stderr. Clean up regress script a bit.
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2018-07-11 09:51:28 -07:00 |
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example_config_freepdk45.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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example_config_scn3me_subm.py
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Clean up new code for add_modules, add_pins and netlist/layouts.
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2018-08-28 10:24:09 -07:00 |
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gen_stimulus.py
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Convert entire OpenRAM to use python3. Works with Python 3.6.
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2018-05-14 16:15:45 -07:00 |
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globals.py
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Add sram_config class. Rename port variables for better description.
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2018-08-31 12:03:28 -07:00 |
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openram.py
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Add sram_config class. Rename port variables for better description.
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2018-08-31 12:03:28 -07:00 |
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options.py
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Add sram_config class. Rename port variables for better description.
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2018-08-31 12:03:28 -07:00 |
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sram.py
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Add sram_config class. Rename port variables for better description.
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2018-08-31 12:03:28 -07:00 |
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sram_1bank.py
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Merging changes and updating multiport syntax across several tests
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2018-09-03 19:36:20 -07:00 |
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sram_2bank.py
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Add sram_config class. Rename port variables for better description.
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2018-08-31 12:03:28 -07:00 |
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sram_4bank.py
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Add sram_config class. Rename port variables for better description.
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2018-08-31 12:03:28 -07:00 |
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sram_base.py
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Merging changes and updating multiport syntax across several tests
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2018-09-03 19:36:20 -07:00 |
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sram_config.py
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Add sram_config class. Rename port variables for better description.
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2018-08-31 12:03:28 -07:00 |
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