| .. |
|
base
|
Comment debug for possible performance issue
|
2018-09-24 11:44:32 -07:00 |
|
characterizer
|
Corrections to functional test that adds multiple cs_b signals per port
|
2018-09-21 09:59:44 -07:00 |
|
gdsMill
|
Add back LEF blockages. Remove "absolute" flags from GDS output
|
2018-09-05 09:28:43 -07:00 |
|
modules
|
Making changes to bank select for multiport. The height of the nor gate using pbitcell was too short and one of the contacts violated drc. Extended height of nor by drc spacing violation so it could pass in multiport.
|
2018-09-27 02:01:32 -07:00 |
|
pgates
|
Replacing replica_pbitcell module with a more effiecient verision. replica_pbitcell is now a wrapper for pbitcell in replica_bitcell mode.
|
2018-09-13 16:53:24 -07:00 |
|
router
|
Remove banks from test configs
|
2018-09-24 11:41:51 -07:00 |
|
tests
|
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
|
2018-09-27 02:02:24 -07:00 |
|
verify
|
Hard code flatten commands for the unique id precharge array
|
2018-09-13 15:15:41 -07:00 |
|
Makefile
|
Add Makefile for parallel test execution.
|
2018-01-22 13:39:07 -08:00 |
|
debug.py
|
Output debug warnings and errors to stderr. Clean up regress script a bit.
|
2018-07-11 09:51:28 -07:00 |
|
example_config_freepdk45.py
|
Remove scn3me lib files. Remove bank references.
|
2018-09-24 11:28:43 -07:00 |
|
example_config_scn4m_subm.py
|
Remove scn3me lib files. Remove bank references.
|
2018-09-24 11:28:43 -07:00 |
|
gen_stimulus.py
|
Convert entire OpenRAM to use python3. Works with Python 3.6.
|
2018-05-14 16:15:45 -07:00 |
|
globals.py
|
Rename omits 0 size ports
|
2018-09-24 13:44:31 -07:00 |
|
openram.py
|
Cleanup some items with new sram_config. Update unit tests accordingly.
|
2018-09-04 10:47:24 -07:00 |
|
options.py
|
Merge branch 'dev' of https://github.com/VLSIDA/PrivateRAM into multiport
|
2018-09-27 02:02:24 -07:00 |
|
sram.py
|
Cleanup some items with new sram_config. Update unit tests accordingly.
|
2018-09-04 10:47:24 -07:00 |
|
sram_1bank.py
|
Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.
|
2018-09-26 19:10:24 -07:00 |
|
sram_2bank.py
|
Cleanup some items with new sram_config. Update unit tests accordingly.
|
2018-09-04 10:47:24 -07:00 |
|
sram_4bank.py
|
Cleanup some items with new sram_config. Update unit tests accordingly.
|
2018-09-04 10:47:24 -07:00 |
|
sram_base.py
|
Editting top level netlist for multiport. Now there are multiple control logic modules, one per port. Since diffent ports are driven by different clocks, also separating dff modules, one per port.
|
2018-09-26 19:10:24 -07:00 |
|
sram_config.py
|
Cleanup some items with new sram_config. Update unit tests accordingly.
|
2018-09-04 10:47:24 -07:00 |
66933ed922