Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 01:24:39 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
5cb3a24b19e0f726e0e220b3583df8518ca671ce
OpenRAM/compiler/router
T
History
Matt Guthaus 5cb3a24b19 Fix supply rail step size to place alternating rails
2018-10-15 13:58:40 -07:00
..
tests
Fix print check regression
2018-10-15 13:23:31 -07:00
direction.py
Routing and connecting rails with vias done.
2018-09-07 14:46:58 -07:00
grid_cell.py
Supply router working except:
2018-09-18 12:57:39 -07:00
grid_path.py
Rewrote pin enclosure code to better address off grid pins.
2018-10-10 15:15:58 -07:00
grid.py
Cleanup of router.
2018-10-04 14:04:29 -07:00
router.py
Fix print check regression
2018-10-15 13:23:31 -07:00
signal_grid.py
Rewrote pin enclosure code to better address off grid pins.
2018-10-10 15:15:58 -07:00
signal_router.py
Cleanup of router.
2018-10-04 14:04:29 -07:00
supply_grid.py
Supply router working except:
2018-09-18 12:57:39 -07:00
supply_router.py
Fix supply rail step size to place alternating rails
2018-10-15 13:58:40 -07:00
vector3d.py
DRC clean supply grid routing on control logic.
2018-09-20 16:00:13 -07:00
Powered by Gitea Version: 1.27.2 Page: 1093ms Template: 15ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API