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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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5bf915a23256370188e5b6c86ff23e3d4a00667e
OpenRAM/compiler/pgates
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Matt Guthaus bab92fcf38 Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.
2018-03-23 08:13:20 -07:00
..
pgate.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
pinv.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
pinvbuf.py
Rework hierarchical decoder to not be folded. Remove address from central bank bus and access via side pins now. Eight way column mux now works.
2018-03-23 08:13:20 -07:00
pnand2.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
pnand3.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
pnor2.py
Fixed comment style on power functions. Also added power parameters to scn3me_subm tech file and tested functionality.
2018-03-01 23:34:15 -08:00
ptx.py
Organize top-level files into subdirs.
2018-02-09 10:25:24 -08:00
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