mirror of https://github.com/VLSIDA/OpenRAM.git
68 lines
3.4 KiB
Python
68 lines
3.4 KiB
Python
#!/usr/bin/env python3
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# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2023 Regents of the University of California
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# All rights reserved.
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#
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from openram import debug
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from openram.modules import bitcell_array, pattern
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from openram.sram_factory import factory
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from openram.base import geometry
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from openram import OPTS
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from .sky130_bitcell_base_array import sky130_bitcell_base_array
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from math import ceil
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class sky130_bitcell_array(bitcell_array, sky130_bitcell_base_array):
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"""
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Creates a rows x cols array of memory cells.
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Assumes bit-lines and word lines are connected by abutment.
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"""
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def __init__(self, rows, cols, column_offset=0, name=""):
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# Don't call the regular bitcell_array constructor since we don't want its constructor, just
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# some of it's useful member functions
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sky130_bitcell_base_array.__init__(self, rows=rows, cols=cols, column_offset=column_offset, name=name)
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if self.row_size % 2 == 0:
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debug.error("Invalid number of rows {}. number of rows (excluding dummy rows) must be odd to connect to col ends".format(self.row_size), -1)
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debug.info(1, "Creating {0} {1} x {2}".format(self.name, self.row_size, self.column_size))
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self.add_comment("rows: {0} cols: {1}".format(self.row_size, self.column_size))
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# This will create a default set of bitline/wordline names
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self.create_all_bitline_names()
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self.create_all_wordline_names()
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self.create_netlist()
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if not OPTS.netlist_only:
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self.create_layout()
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self.add_supply_pins()
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def add_modules(self):
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""" Add the modules used in this design """
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# Bitcell for port names only
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self.cell = factory.create(module_type=OPTS.bitcell, version="opt1")
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self.cella = factory.create(module_type=OPTS.bitcell, version="opt1a")
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self.strap = factory.create(module_type="internal", version="wlstrap")
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self.strap_p = factory.create(module_type="internal", version="wlstrap_p")
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self.strapa = factory.create(module_type="internal", version="wlstrapa")
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self.strapa_p = factory.create(module_type="internal", version="wlstrapa_p")
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def create_instances(self):
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""" Create the module instances used in this design """
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self.all_inst={}
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self.cell_inst={}
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bit_row_opt1 = [geometry.instance("00_opt1", mod=self.cell, is_bitcell=True)] \
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+ [geometry.instance("01_strap", mod=self.strap, is_bitcell=False)]\
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+ [geometry.instance("02_opt1", mod=self.cell, is_bitcell=True)] \
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+ [geometry.instance("03_strap_p", mod=self.strap_p, is_bitcell=False)]
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bit_row_opt1a = [geometry.instance("10_opt1a", mod=self.cella, is_bitcell=True)] \
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+ [geometry.instance("11_strapa", mod=self.strapa, is_bitcell=False)] \
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+ [geometry.instance("12_opt1a", mod=self.cella, is_bitcell=True)] \
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+ [geometry.instance("13_strapa_p", mod=self.strapa_p, is_bitcell=False)]
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bit_block = []
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pattern.append_row_to_block(bit_block, bit_row_opt1)
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pattern.append_row_to_block(bit_block, bit_row_opt1a)
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self.pattern = pattern(self, "bitcell_array", bit_block, num_rows=self.row_size, num_cols=self.column_size, num_cores_x=ceil(self.row_size/2), name_template="bit_r{0}_c{1}")
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self.pattern.connect_array()
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