OpenRAM/compiler/router
mrg 7b8c2cac30 Starting single layer power router. 2019-06-03 15:28:55 -07:00
..
tests Update copyright to correct years. 2019-05-06 06:50:15 -07:00
direction.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
grid.py Starting single layer power router. 2019-06-03 15:28:55 -07:00
grid_cell.py Starting single layer power router. 2019-06-03 15:28:55 -07:00
grid_path.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
grid_utils.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
pin_group.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
router.py Starting single layer power router. 2019-06-03 15:28:55 -07:00
router_tech.py Starting single layer power router. 2019-06-03 15:28:55 -07:00
signal_grid.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
signal_router.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
supply_grid.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00
supply_grid_router.py Begin single layer supply router 2019-06-03 15:27:37 -07:00
supply_tree_router.py Starting single layer power router. 2019-06-03 15:28:55 -07:00
vector3d.py Update copyright to correct years. 2019-05-06 06:50:15 -07:00