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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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55ed6212a1ec67ff3f1be7c9ccc1e3c8d478153b
OpenRAM/compiler/router
T
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Matt Guthaus 55ed6212a1 Created route and add_route for layer assigned wires. It will replace add_wire/wire eventually.
2017-04-19 12:41:13 -07:00
..
tests
Created route and add_route for layer assigned wires. It will replace add_wire/wire eventually.
2017-04-19 12:41:13 -07:00
cell.py
Contract path to simplified route
2016-11-17 13:26:03 -08:00
grid.py
Fixed router test 03. Cleaned up code.
2017-04-14 13:56:09 -07:00
regress.sh
Added regress script for router
2016-11-18 11:21:39 -08:00
router.py
Created route and add_route for layer assigned wires. It will replace add_wire/wire eventually.
2017-04-19 12:41:13 -07:00
vector3d.py
Routing multilayer, around blockages.
2016-11-16 16:47:31 -08:00
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