Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-02 02:57:53 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
54bd022efc83de17cc3d90dfbacf2afd19c2a84d
OpenRAM/technology/scn4m_subm/gds_lib
T
History
mrg 12a6f1f2ee Add missing well tap
2022-02-25 10:44:40 -08:00
..
cell_1rw.gds
Rework bitcells.
2020-11-13 10:07:40 -08:00
cell_2rw.gds
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
dff.gds
update gds library, generalize geometry reverse transform function
2019-12-24 05:01:55 +00:00
dummy_cell_1rw.gds
Rework bitcells.
2020-11-13 10:07:40 -08:00
dummy_cell_2rw.gds
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
replica_cell_1rw.gds
Remove label Q_bar from replica_cell_1rw due to Magic port bug
2022-01-13 14:38:59 -08:00
replica_cell_2rw.gds
Convert bitcells to 1port and 2port
2020-11-13 08:09:21 -08:00
sense_amp.gds
update gds library, generalize geometry reverse transform function
2019-12-24 05:01:55 +00:00
tri_gate.gds
update gds library, generalize geometry reverse transform function
2019-12-24 05:01:55 +00:00
write_driver.gds
Add missing well tap
2022-02-25 10:44:40 -08:00
Powered by Gitea Version: 1.27.2 Page: 180ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API