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luke
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OpenRAM
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https://github.com/VLSIDA/OpenRAM.git
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2026-08-29 01:24:39 +02:00
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541d4ff572f333c3ed42630cfb65f592a3df862e
OpenRAM
/
technology
/
freepdk45
/
tech
T
History
Jesse Cirimelli-Low
541d4ff572
parameterize how power ring is connected to crba
2026-05-06 09:50:56 -07:00
..
__init__.py
Update copyright year
2023-01-28 22:56:27 -08:00
freepdk45.lydrc
Do not run same well spacing for backwards compatibility. Add pbitcell cheat.
2021-11-22 11:33:27 -08:00
freepdk45.lylvs
By default uniquify instances based on macro name.
2022-03-11 18:01:45 -08:00
freepdk45.lyp
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
freepdk45.lyt
Initial klayout DRC/LVS options
2021-09-07 16:51:16 -07:00
scn4m_subm.lyp
Add DRC rules and display files
2021-11-22 11:33:27 -08:00
scn4m_subm.lyt
Add DRC rules and display files
2021-11-22 11:33:27 -08:00
tech.py
parameterize how power ring is connected to crba
2026-05-06 09:50:56 -07:00
