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OpenRAM/compiler/tests
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Jesse Cirimelli-Low 53d53ec271 checkpoint from tt submission
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..
configs
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golden
single port fixes
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sp_files
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00_code_format_check_test.py
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01_library_test.py
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03_contact_test.py
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03_path_test.py
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03_ptx_1finger_nmos_test.py
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03_ptx_1finger_pmos_test.py
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03_ptx_3finger_nmos_test.py
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03_ptx_3finger_pmos_test.py
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03_ptx_4finger_nmos_test.py
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03_ptx_4finger_pmos_test.py
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03_ptx_no_contacts_test.py
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03_wire_test.py
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04_and2_dec_test.py
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04_and3_dec_test.py
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04_and4_dec_test.py
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04_column_mux_1rw_1r_test.py
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04_column_mux_pbitcell_test.py
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04_column_mux_test.py
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04_dff_buf_test.py
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04_dummy_pbitcell_1rw1r1w_test.py
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04_dummy_pbitcell_1rw_test.py
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04_pand2_test.py
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04_pand3_test.py
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04_pand4_test.py
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04_pbitcell_test.py
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04_pbuf_dec_8x_test.py
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04_pbuf_test.py
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04_pdriver_test.py
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04_pinv_1x_beta_test.py
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04_pinv_1x_test.py
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04_pinv_2x_test.py
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04_pinv_10x_test.py
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04_pinv_100x_test.py
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04_pinv_dec_1x_test.py
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04_pinvbuf_test.py
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04_pnand2_test.py
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04_pnand3_test.py
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04_pnand4_test.py
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04_pnor2_test.py
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04_precharge_1rw_1r_test.py
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04_precharge_pbitcell_test.py
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04_precharge_test.py
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04_pwrite_driver_test.py
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04_replica_pbitcell_1rw1r1w_test.py
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04_replica_pbitcell_1rw_test.py
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04_rom_address_control_buf_test.py
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04_rom_precharge_test.py
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04_wordline_driver_test.py
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05_bitcell_array_1rw_1r_test.py
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05_bitcell_array_test.py
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05_dummy_array_test.py
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05_pbitcell_array_test.py
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05_rom_array_test.py
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06_column_decoder_16row_test.py
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06_hierarchical_decoder_16row_1rw_1r_test.py
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06_hierarchical_decoder_16row_test.py
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06_hierarchical_decoder_17row_1rw_1r_test.py
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06_hierarchical_decoder_17row_test.py
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06_hierarchical_decoder_32row_1rw_1r_test.py
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06_hierarchical_decoder_32row_test.py
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06_hierarchical_decoder_64row_1rw_1r_test.py
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06_hierarchical_decoder_64row_test.py
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06_hierarchical_decoder_132row_1rw_1r_test.py
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06_hierarchical_decoder_132row_test.py
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06_hierarchical_decoder_512row_1rw_1r_test.py
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06_hierarchical_decoder_512row_test.py
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06_hierarchical_decoder_4096row_1rw_1r_test.py
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06_hierarchical_decoder_4096row_test.py
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06_hierarchical_decoder_pbitcell_test.py
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06_hierarchical_predecode2x4_1rw_1r_test.py
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06_hierarchical_predecode2x4_pbitcell_test.py
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06_hierarchical_predecode2x4_test.py
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06_hierarchical_predecode3x8_1rw_1r_test.py
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06_hierarchical_predecode3x8_pbitcell_test.py
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06_hierarchical_predecode3x8_test.py
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06_hierarchical_predecode4x16_test.py
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06_rom_decoder_test.py
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07_column_mux_array_2mux_1rw_1r_test.py
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07_column_mux_array_2mux_test.py
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07_column_mux_array_4mux_1rw_1r_test.py
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07_column_mux_array_4mux_test.py
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07_column_mux_array_8mux_1rw_1r_test.py
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07_column_mux_array_8mux_test.py
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07_column_mux_array_16mux_1rw_1r_test.py
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07_column_mux_array_16mux_test.py
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07_column_mux_array_pbitcell_test.py
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07_rom_column_mux_array_test.py
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08_precharge_array_1rw_1r_test.py
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08_precharge_array_test.py
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08_rom_decoder_buffer_array_test.py
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08_rom_precharge_array_test.py
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08_wordline_buffer_array_test.py
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08_wordline_driver_array_1rw_1r_test.py
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08_wordline_driver_array_pbitcell_test.py
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08_wordline_driver_array_test.py
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09_sense_amp_array_1rw_1r_test.py
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09_sense_amp_array_pbitcell_test.py
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09_sense_amp_array_spare_cols_test.py
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09_sense_amp_array_test.py
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10_rom_wordline_driver_array_test.py
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10_write_driver_array_1rw_1r_test.py
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10_write_driver_array_pbitcell_test.py
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10_write_driver_array_spare_cols_test.py
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10_write_driver_array_test.py
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10_write_driver_array_wmask_pbitcell_test.py
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10_write_driver_array_wmask_spare_cols_test.py
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10_write_driver_array_wmask_test.py
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10_write_mask_and_array_1rw_1r_test.py
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10_write_mask_and_array_pbitcell_test.py
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10_write_mask_and_array_test.py
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11_dff_array_test.py
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11_dff_buf_array_test.py
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12_tri_gate_array_test.py
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13_delay_chain_test.py
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14_capped_replica_bitcell_array_bothrbl_1rw_1r_test.py
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14_capped_replica_bitcell_array_dummies_1rw_1r_test.py
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14_capped_replica_bitcell_array_dummies_1rw_test.py
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14_capped_replica_bitcell_array_leftrbl_1rw_1r_test.py
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14_capped_replica_bitcell_array_leftrbl_1rw_test.py
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14_capped_replica_bitcell_array_norbl_1rw_1r_test.py
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14_capped_replica_bitcell_array_norbl_1rw_test.py
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14_capped_replica_bitcell_array_rightrbl_1rw_1r_test.py
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14_replica_bitcell_array_bothrbl_1rw_1r_test.py
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14_replica_bitcell_array_dummies_1rw_1r_test.py
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14_replica_bitcell_array_dummies_1rw_test.py
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14_replica_bitcell_array_leftrbl_1rw_1r_test.py
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14_replica_bitcell_array_leftrbl_1rw_test.py
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14_replica_bitcell_array_norbl_1rw_1r_test.py
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14_replica_bitcell_array_norbl_1rw_test.py
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14_replica_bitcell_array_rightrbl_1rw_1r_test.py
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14_replica_column_1rw_1r_test.py
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14_replica_column_1rw_test.py
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14_replica_pbitcell_1rw1r_array_test.py
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14_replica_pbitcell_1rw_array_test.py
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15_global_bitcell_array_norbl_1rw_1r_test.py
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15_global_bitcell_array_norbl_1rw_test.py
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15_global_bitcell_array_rbl_1rw_1r_test.py
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15_global_bitcell_array_rbl_1rw_test.py
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15_local_bitcell_array_bothrbl_1rw_1r_test.py
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15_local_bitcell_array_dummies_1rw_1r_test.py
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15_local_bitcell_array_dummies_1rw_test.py
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15_local_bitcell_array_leftrbl_1rw_1r_test.py
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15_local_bitcell_array_leftrbl_1rw_test.py
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15_local_bitcell_array_norbl_1rw_1r_test.py
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15_local_bitcell_array_norbl_1rw_test.py
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15_local_bitcell_array_rightrbl_1rw_1r_test.py
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16_control_logic_delay_multiport_test.py
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16_control_logic_delay_r_test.py
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16_control_logic_delay_rw_test.py
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16_control_logic_delay_w_test.py
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16_control_logic_multiport_test.py
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16_control_logic_r_test.py
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16_control_logic_rw_test.py
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16_control_logic_w_test.py
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16_rom_control_logic_test.py
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18_port_address_16rows_1rw_1r_test.py
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18_port_address_16rows_test.py
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18_port_address_256rows_1rw_1r_test.py
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18_port_address_512rows_test.py
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18_port_data_2mux_1rw_1r_test.py
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18_port_data_2mux_test.py
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18_port_data_4mux_1rw_1r_test.py
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18_port_data_4mux_test.py
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18_port_data_8mux_1rw_1r_test.py
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18_port_data_8mux_test.py
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18_port_data_16mux_1rw_1r_test.py
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18_port_data_16mux_test.py
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18_port_data_nomux_1rw_1r_test.py
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18_port_data_nomux_test.py
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18_port_data_spare_cols_test.py
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18_port_data_wmask_1rw_1r_test.py
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18_port_data_wmask_test.py
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19_multi_bank_test.py
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19_pmulti_bank_test.py
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19_psingle_bank_test.py
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19_rom_bank_test.py
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19_single_bank_1w_1r_test.py
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19_single_bank_2mux_1rw_1r_test.py
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19_single_bank_2mux_test.py
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19_single_bank_4mux_1rw_1r_test.py
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19_single_bank_4mux_test.py
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19_single_bank_8mux_1rw_1r_test.py
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19_single_bank_8mux_test.py
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19_single_bank_16mux_1rw_1r_test.py
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19_single_bank_16mux_test.py
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19_single_bank_global_bitline_test.py
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19_single_bank_nomux_1rw_1r_test.py
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19_single_bank_nomux_norbl_1rw_1r_test.py
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19_single_bank_nomux_norbl_test.py
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19_single_bank_nomux_test.py
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19_single_bank_spare_cols_test.py
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19_single_bank_wmask_1rw_1r_test.py
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19_single_bank_wmask_test.py
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20_psram_1bank_2mux_1rw_1w_test.py
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20_psram_1bank_2mux_1rw_1w_wmask_test.py
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20_psram_1bank_2mux_1w_1r_test.py
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20_psram_1bank_2mux_test.py
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20_psram_1bank_4mux_1rw_1r_test.py
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20_sram_1bank_2mux_1rw_1r_spare_cols_test.py
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20_sram_1bank_2mux_1rw_1r_test.py
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20_sram_1bank_2mux_1w_1r_spare_cols_test.py
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20_sram_1bank_2mux_1w_1r_test.py
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20_sram_1bank_2mux_global_test.py
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20_sram_1bank_2mux_test.py
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20_sram_1bank_2mux_wmask_spare_cols_test.py
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20_sram_1bank_2mux_wmask_test.py
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20_sram_1bank_4mux_1rw_1r_test.py
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20_sram_1bank_4mux_test.py
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20_sram_1bank_8mux_1rw_1r_test.py
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20_sram_1bank_8mux_test.py
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20_sram_1bank_16mux_1rw_1r_test.py
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20_sram_1bank_16mux_test.py
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20_sram_1bank_32b_1024_wmask_test.py
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20_sram_1bank_nomux_1rw_1r_spare_cols_test.py
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20_sram_1bank_nomux_1rw_1r_test.py
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20_sram_1bank_nomux_norbl_1rw_1r_test.py
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20_sram_1bank_nomux_norbl_test.py
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20_sram_1bank_nomux_test.py
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20_sram_1bank_nomux_wmask_sparecols_test.py
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20_sram_1bank_nomux_wmask_test.py
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20_sram_1bank_ring_test.py
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20_sram_2bank_test.py
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22_psram_1bank_2mux_func_test.py
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22_psram_1bank_8mux_func_test.py
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22_psram_1bank_nomux_func_test.py
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22_sram_1bank_2mux_func_test.py
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22_sram_1bank_2mux_global_func_test.py
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22_sram_1bank_2mux_sparecols_func_test.py
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22_sram_1bank_4mux_func_test.py
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22_sram_1bank_8mux_func_test.py
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22_sram_1bank_nomux_1rw_1r_func_test.py
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22_sram_1bank_nomux_func_test.py
Merge branch 'singleport_refactor' into array_gen
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22_sram_1bank_nomux_sparecols_func_test.py
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22_sram_1bank_wmask_1rw_1r_func_test.py
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22_sram_wmask_func_test.py
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23_lib_sram_linear_regression_test.py
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23_lib_sram_model_corners_test.py
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24_lef_sram_test.py
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25_verilog_multibank_test.py
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25_verilog_sram_test.py
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26_hspice_pex_pinv_test.py
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26_ngspice_pex_pinv_test.py
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30_openram_back_end_library_test.py
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30_openram_sram_func_test.py
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50_riscv_1k_1rw1r_func_test.py
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50_riscv_1k_1rw_func_test.py
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50_riscv_1rw1r_phys_test.py
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50_riscv_2k_1rw1r_func_test.py
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50_riscv_4k_1rw1r_func_test.py
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50_riscv_512b_1rw1r_func_test.py
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50_riscv_512b_1rw_func_test.py
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Makefile
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sram_1rw_1r_tb.v
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sram_1rw_tb.v
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sram_1rw_wmask_tb.v
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testutils.py
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