Matt Guthaus 53c72c6054 Merge branch 'tech_migration' of github.com:VLSIDA/PrivateRAM into tech_migration

2019-12-05 15:41:56 -08:00

..

contact.py

Add contact variation

2019-12-05 15:38:25 -08:00

delay_data.py

Remove some flake8 errors/warnings.

2019-10-02 23:26:02 +00:00

design.py

Updates to gdsMill/tech layers

2019-12-04 16:12:53 -08:00

geometry.py

Updates to gdsMill/tech layers

2019-12-04 16:12:53 -08:00

graph_util.py

Made all cin function relate to farads and all input_load relate to relative units.

2019-08-08 01:57:04 -07:00

hierarchy_design.py

Allow gds to be written with supplies off. Fix extraction bug with new options.

2019-09-03 11:23:35 -07:00

hierarchy_layout.py

Decrease verbosity of boundary layer

2019-12-05 23:33:23 +00:00

hierarchy_spice.py

Share nominal temperature and voltage. Nominal instead of typical.

2019-09-04 16:53:58 -07:00

lef.py

Added functionality to express polygons in LEF files.

2019-06-25 09:20:00 -07:00

pin_layout.py

Updates to gdsMill/tech layers

2019-12-04 16:12:53 -08:00

power_data.py

Move classes to individual file.

2019-07-16 15:18:04 -07:00

route.py

Fix space before comment

2019-06-14 08:43:41 -07:00

utils.py

Add layer-purpose GDS support. Various PEP8 fixes.

2019-11-14 18:17:20 +00:00

vector.py

Fix space before comment

2019-06-14 08:43:41 -07:00

verilog.py

Feedthru port edits.

2019-09-27 14:18:49 -07:00

wire_path.py

Fix space before comment

2019-06-14 08:43:41 -07:00

wire_spice_model.py

Move classes to individual file.

2019-07-16 15:18:04 -07:00

wire.py

Fix space before comment

2019-06-14 08:43:41 -07:00