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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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537fd6eff9dc0f1980dfebf442d59f1ab8664023
OpenRAM/compiler/router
T
History
mrg 1ded978256 Change nwell from gnd to vdd. dnwell space added.
2021-06-01 15:10:55 -07:00
..
direction.py
PEP8 cleanup
2021-02-23 13:32:13 -08:00
grid_cell.py
Update copyright year.
2021-01-22 11:23:28 -08:00
grid_path.py
Update copyright year.
2021-01-22 11:23:28 -08:00
grid_utils.py
Update copyright year.
2021-01-22 11:23:28 -08:00
grid.py
Improve supply routing for ring and side pins
2021-05-28 10:58:30 -07:00
pin_group.py
Add left stripe power routes to tree router as option.
2021-05-05 13:45:12 -07:00
router_tech.py
Add left stripe power routes to tree router as option.
2021-05-05 13:45:12 -07:00
router.py
Change nwell from gnd to vdd. dnwell space added.
2021-06-01 15:10:55 -07:00
signal_escape_router.py
Add left stripe power routes to tree router as option.
2021-05-05 13:45:12 -07:00
signal_grid.py
Update copyright year.
2021-01-22 11:23:28 -08:00
signal_router.py
Add left stripe power routes to tree router as option.
2021-05-05 13:45:12 -07:00
supply_grid_router.py
Separate supply pin type from route supplies option
2021-05-28 11:55:50 -07:00
supply_grid.py
Update copyright year.
2021-01-22 11:23:28 -08:00
supply_tree_router.py
Remove debug gds dump
2021-05-28 13:31:19 -07:00
vector3d.py
Add dnwell
2021-05-26 16:14:16 -07:00
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