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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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504f9aa8928dcea308ef4f56afa8ba8e2ee0919f
OpenRAM/compiler/characterizer
T
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Hunter Nichols 56c4c89720 Adjusted error margin for period in analytical model and added check in model test.
2020-12-17 01:34:53 -08:00
..
__init__.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
bit_polarity.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
charutils.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
delay.py
Adjusted error margin for period in analytical model and added check in model test.
2020-12-17 01:34:53 -08:00
functional.py
Output functional stimulus to output directory.
2020-11-09 12:00:25 -08:00
lib.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
logical_effort.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
measurements.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
model_check.py
Changed named on delay chain sizing variable. Automatic sizing default is False.
2020-11-17 14:29:01 -08:00
setup_hold.py
Add custom cell custom port order code. Update setup/hold to use it.
2020-11-17 11:12:59 -08:00
simulation.py
Fixed issue with selection of column address when checking bitline names.
2020-11-20 01:11:08 -08:00
sram_op.py
Clean up. Split class into own file.
2019-07-24 08:15:10 -07:00
stimuli.py
Don't check for file to determine if it is included.
2020-11-09 12:11:47 -08:00
trim_spice.py
Remove EOL whitespace globally
2020-11-03 06:29:17 -08:00
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