mrg 11a82b7283 Fixed local bitcell array for single and dual port

2020-08-27 14:03:05 -07:00

..

channel_route.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

contact.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

custom_cell_properties.py

sense_amp: Allow custom pin names

2020-02-17 15:20:12 +01:00

delay_data.py

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design.py

Comment updates

2020-08-17 14:35:39 -07:00

errors.py

Add exception errors file

2020-04-08 16:55:45 -07:00

geometry.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

graph_util.py

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hierarchy_design.py

Default drc and lvs errors is skipped.

2020-07-13 14:08:00 -07:00

hierarchy_layout.py

Add parent to channel route for dumpign debug gds.

2020-07-20 12:03:25 -07:00

hierarchy_spice.py

Fixed local bitcell array for single and dual port

2020-08-27 14:03:05 -07:00

lef.py

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pin_layout.py

Only do reverse lookup on valid interconnect layers since layer numbers can be shared.

2020-06-29 14:42:24 -07:00

power_data.py

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route.py

Change inheritance inits to use super

2020-08-06 11:33:26 -07:00

utils.py

s8 gdsless netlist only working up to dff array

2020-02-09 21:37:09 -08:00

vector.py

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verilog.py

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wire_path.py

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00

wire_spice_model.py

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wire.py

Changes to simplify metal preferred directions and pitches.

2020-05-10 11:32:45 -07:00