OpenRAM/technology/sky130/tech
Jesse Cirimelli-Low 03c5a58758 add sp non cypress bitcells 2026-05-04 12:47:00 -07:00
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gds_lib add sp non cypress bitcells 2026-05-04 12:47:00 -07:00
sp_lib add sp non cypress bitcells 2026-05-04 12:47:00 -07:00
tech_configs all sky130 crba passing 2026-04-28 23:22:40 -07:00
__init__.py Update copyright year 2023-01-28 22:56:27 -08:00
sky130.lydrc Add initial sky130 LVS/DRC rules. 2021-12-17 10:27:13 -08:00
sky130.lylvs Add initial sky130 LVS/DRC rules. 2021-12-17 10:27:13 -08:00
tech.py squash commits 2026-04-22 01:33:47 -07:00