| .. |
|
and2_dec.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
and3_dec.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
and4_dec.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
bank.py
|
Add hierarchical seperator option to work with Xyce measurements.
|
2021-05-14 16:16:25 -07:00 |
|
bank_select.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
bitcell_array.py
|
Add hierarchical seperator option to work with Xyce measurements.
|
2021-05-14 16:16:25 -07:00 |
|
bitcell_base_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
col_cap_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
column_mux_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
control_logic.py
|
Fix placement of delay chain to align with control logic rows.
|
2021-05-05 14:21:53 -07:00 |
|
delay_chain.py
|
Fix Verilog module typo. Adjust RBL route.
|
2021-05-06 14:32:47 -07:00 |
|
dff_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_buf.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_buf_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_inv.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dff_inv_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
dummy_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
global_bitcell_array.py
|
Add hierarchical seperator option to work with Xyce measurements.
|
2021-05-14 16:16:25 -07:00 |
|
hierarchical_decoder.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
hierarchical_predecode.py
|
Respect the bus spacing parameter in predecoder.
|
2021-04-19 10:51:16 -07:00 |
|
hierarchical_predecode2x4.py
|
Skywater changes.
|
2021-03-22 15:48:14 -07:00 |
|
hierarchical_predecode3x8.py
|
Skywater changes.
|
2021-03-22 15:48:14 -07:00 |
|
hierarchical_predecode4x16.py
|
Skywater changes.
|
2021-03-22 15:48:14 -07:00 |
|
local_bitcell_array.py
|
Add hierarchical seperator option to work with Xyce measurements.
|
2021-05-14 16:16:25 -07:00 |
|
module_type.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
multibank.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
orig_bitcell_array.py
|
Add hierarchical seperator option to work with Xyce measurements.
|
2021-05-14 16:16:25 -07:00 |
|
port_address.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
port_data.py
|
Use OPTS.precharge instead of hard coded precharge.
|
2021-03-15 09:44:14 -07:00 |
|
precharge_array.py
|
Use OPTS.precharge instead of hard coded precharge.
|
2021-03-15 09:44:14 -07:00 |
|
replica_bitcell_array.py
|
Add hierarchical seperator option to work with Xyce measurements.
|
2021-05-14 16:16:25 -07:00 |
|
replica_column.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
row_cap_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
sense_amp_array.py
|
Remove vertical power pin vias.
|
2021-02-23 13:32:00 -08:00 |
|
tri_gate_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
wordline_buffer_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
wordline_driver_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
write_driver_array.py
|
Update copyright year.
|
2021-01-22 11:23:28 -08:00 |
|
write_mask_and_array.py
|
Add via when write driver supply is different layer
|
2021-04-28 15:16:26 -07:00 |
3abebe4068