mirror of https://github.com/VLSIDA/OpenRAM.git
287 lines
12 KiB
Python
287 lines
12 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import design
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import math
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import contact
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from vector import vector
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from sram_factory import factory
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class hierarchical_predecode(design.design):
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"""
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Pre 2x4 and 3x8 decoder shared code.
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"""
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def __init__(self, name, input_number, height=None):
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self.number_of_inputs = input_number
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self.cell_height = height
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self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
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design.design.__init__(self, name)
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def add_pins(self):
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for k in range(self.number_of_inputs):
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self.add_pin("in_{0}".format(k), "INPUT")
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for i in range(self.number_of_outputs):
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self.add_pin("out_{0}".format(i), "OUTPUT")
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self.add_pin("vdd", "POWER")
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self.add_pin("gnd", "GROUND")
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def add_modules(self):
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""" Add the INV and NAND gate modules """
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self.inv = factory.create(module_type="pinv",
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height=self.cell_height)
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self.add_mod(self.inv)
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self.add_nand(self.number_of_inputs)
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self.add_mod(self.nand)
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def add_nand(self, inputs):
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""" Create the NAND for the predecode input stage """
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if inputs==2:
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self.nand = factory.create(module_type="pnand2",
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height=self.cell_height)
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elif inputs==3:
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self.nand = factory.create(module_type="pnand3",
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height=self.cell_height)
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else:
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debug.error("Invalid number of predecode inputs: {}".format(inputs), -1)
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def setup_layout_constraints(self):
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self.height = self.number_of_outputs * self.nand.height
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# x offset for input inverters
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self.x_off_inv_1 = self.number_of_inputs*self.m2_pitch
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# x offset to NAND decoder includes the left rails, mid rails and inverters, plus two extra m2 pitches
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self.x_off_nand = self.x_off_inv_1 + self.inv.width + (2*self.number_of_inputs + 2) * self.m2_pitch
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# x offset to output inverters
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self.x_off_inv_2 = self.x_off_nand + self.nand.width
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# Height width are computed
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self.width = self.x_off_inv_2 + self.inv.width
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def route_rails(self):
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""" Create all of the rails for the inputs and vdd/gnd/inputs_bar/inputs """
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input_names = ["in_{}".format(x) for x in range(self.number_of_inputs)]
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offset = vector(0.5*self.m2_width,2*self.m1_width)
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self.input_rails = self.create_vertical_pin_bus(layer="m2",
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pitch=self.m2_pitch,
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offset=offset,
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names=input_names,
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length=self.height - 2*self.m1_width)
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invert_names = ["Abar_{}".format(x) for x in range(self.number_of_inputs)]
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non_invert_names = ["A_{}".format(x) for x in range(self.number_of_inputs)]
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decode_names = invert_names + non_invert_names
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offset = vector(self.x_off_inv_1 + self.inv.width + 2*self.m2_pitch, 2*self.m1_width)
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self.decode_rails = self.create_vertical_bus(layer="m2",
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pitch=self.m2_pitch,
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offset=offset,
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names=decode_names,
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length=self.height - 2*self.m1_width)
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def create_input_inverters(self):
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""" Create the input inverters to invert input signals for the decode stage. """
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self.in_inst = []
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for inv_num in range(self.number_of_inputs):
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name = "pre_inv_{0}".format(inv_num)
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self.in_inst.append(self.add_inst(name=name,
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mod=self.inv))
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self.connect_inst(["in_{0}".format(inv_num),
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"inbar_{0}".format(inv_num),
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"vdd", "gnd"])
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def place_input_inverters(self):
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""" Place the input inverters to invert input signals for the decode stage. """
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for inv_num in range(self.number_of_inputs):
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if (inv_num % 2 == 0):
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y_off = inv_num * (self.inv.height)
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mirror = "R0"
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else:
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y_off = (inv_num + 1) * (self.inv.height)
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mirror="MX"
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offset = vector(self.x_off_inv_1, y_off)
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self.in_inst[inv_num].place(offset=offset,
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mirror=mirror)
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def create_output_inverters(self):
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""" Create inverters for the inverted output decode signals. """
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self.inv_inst = []
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for inv_num in range(self.number_of_outputs):
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name = "pre_nand_inv_{}".format(inv_num)
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self.inv_inst.append(self.add_inst(name=name,
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mod=self.inv))
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self.connect_inst(["Z_{}".format(inv_num),
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"out_{}".format(inv_num),
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"vdd", "gnd"])
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def place_output_inverters(self):
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""" Place inverters for the inverted output decode signals. """
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for inv_num in range(self.number_of_outputs):
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if (inv_num % 2 == 0):
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y_off = inv_num * self.inv.height
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mirror = "R0"
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else:
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y_off =(inv_num + 1)*self.inv.height
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mirror = "MX"
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offset = vector(self.x_off_inv_2, y_off)
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self.inv_inst[inv_num].place(offset=offset,
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mirror=mirror)
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def create_nand_array(self,connections):
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""" Create the NAND stage for the decodes """
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self.nand_inst = []
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for nand_input in range(self.number_of_outputs):
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inout = str(self.number_of_inputs)+"x"+str(self.number_of_outputs)
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name = "Xpre{0}_nand_{1}".format(inout,nand_input)
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self.nand_inst.append(self.add_inst(name=name,
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mod=self.nand))
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self.connect_inst(connections[nand_input])
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def place_nand_array(self):
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""" Place the NAND stage for the decodes """
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for nand_input in range(self.number_of_outputs):
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inout = str(self.number_of_inputs)+"x"+str(self.number_of_outputs)
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if (nand_input % 2 == 0):
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y_off = nand_input * self.inv.height
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mirror = "R0"
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else:
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y_off = (nand_input + 1) * self.inv.height
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mirror = "MX"
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offset = vector(self.x_off_nand, y_off)
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self.nand_inst[nand_input].place(offset=offset,
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mirror=mirror)
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def route(self):
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self.route_input_inverters()
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self.route_inputs_to_rails()
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self.route_nand_to_rails()
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self.route_output_inverters()
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self.route_vdd_gnd()
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def route_inputs_to_rails(self):
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""" Route the uninverted inputs to the second set of rails """
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for num in range(self.number_of_inputs):
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# route one signal next to each vdd/gnd rail since this is
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# typically where the p/n devices are and there are no
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# pins in the nand gates.
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y_offset = (num+self.number_of_inputs) * self.inv.height + contact.m1_via.width + self.m1_space
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in_pin = "in_{}".format(num)
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a_pin = "A_{}".format(num)
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in_pos = vector(self.input_rails[in_pin].x,y_offset)
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a_pos = vector(self.decode_rails[a_pin].x,y_offset)
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self.add_path("m1",[in_pos, a_pos])
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self.add_via_center(layers = self.m1_stack,
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offset=[self.input_rails[in_pin].x, y_offset])
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self.add_via_center(layers = self.m1_stack,
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offset=[self.decode_rails[a_pin].x, y_offset])
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def route_output_inverters(self):
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"""
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Route all conections of the outputs inverters
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"""
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for num in range(self.number_of_outputs):
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# route nand output to output inv input
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zr_pos = self.nand_inst[num].get_pin("Z").rc()
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al_pos = self.inv_inst[num].get_pin("A").lc()
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# ensure the bend is in the middle
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mid1_pos = vector(0.5*(zr_pos.x+al_pos.x), zr_pos.y)
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mid2_pos = vector(0.5*(zr_pos.x+al_pos.x), al_pos.y)
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self.add_path("m1", [zr_pos, mid1_pos, mid2_pos, al_pos])
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z_pin = self.inv_inst[num].get_pin("Z")
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self.add_layout_pin(text="out_{}".format(num),
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layer="m1",
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offset=z_pin.ll(),
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height=z_pin.height(),
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width=z_pin.width())
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def route_input_inverters(self):
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"""
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Route all conections of the inputs inverters [Inputs, outputs, vdd, gnd]
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"""
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for inv_num in range(self.number_of_inputs):
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out_pin = "Abar_{}".format(inv_num)
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in_pin = "in_{}".format(inv_num)
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#add output so that it is just below the vdd or gnd rail
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# since this is where the p/n devices are and there are no
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# pins in the nand gates.
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y_offset = (inv_num+1) * self.inv.height - 3*self.m1_space
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inv_out_pos = self.in_inst[inv_num].get_pin("Z").rc()
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right_pos = inv_out_pos + vector(self.inv.width - self.inv.get_pin("Z").lx(),0)
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rail_pos = vector(self.decode_rails[out_pin].x,y_offset)
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self.add_path("m1", [inv_out_pos, right_pos, vector(right_pos.x, y_offset), rail_pos])
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self.add_via_center(layers = self.m1_stack,
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offset=rail_pos)
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#route input
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inv_in_pos = self.in_inst[inv_num].get_pin("A").lc()
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in_pos = vector(self.input_rails[in_pin].x,inv_in_pos.y)
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self.add_path("m1", [in_pos, inv_in_pos])
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self.add_via_center(layers=self.m1_stack,
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offset=in_pos)
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def route_nand_to_rails(self):
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# This 2D array defines the connection mapping
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nand_input_line_combination = self.get_nand_input_line_combination()
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for k in range(self.number_of_outputs):
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# create x offset list
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index_lst= nand_input_line_combination[k]
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if self.number_of_inputs == 2:
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gate_lst = ["A","B"]
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else:
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gate_lst = ["A","B","C"]
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# this will connect pins A,B or A,B,C
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for rail_pin,gate_pin in zip(index_lst,gate_lst):
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pin_pos = self.nand_inst[k].get_pin(gate_pin).lc()
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rail_pos = vector(self.decode_rails[rail_pin].x, pin_pos.y)
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self.add_path("m1", [rail_pos, pin_pos])
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self.add_via_center(layers=self.m1_stack,
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offset=rail_pos)
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def route_vdd_gnd(self):
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""" Add a pin for each row of vdd/gnd which are must-connects next level up. """
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# Find the x offsets for where the vias/pins should be placed
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in_xoffset = self.in_inst[0].rx() + self.m1_space
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out_xoffset = self.inv_inst[0].lx() - self.m1_space
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for num in range(0,self.number_of_outputs):
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# this will result in duplicate polygons for rails, but who cares
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# Route both supplies
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for n in ["vdd", "gnd"]:
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nand_pin = self.nand_inst[num].get_pin(n)
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supply_offset = nand_pin.ll().scale(0,1)
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self.add_rect(layer="m1",
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offset=supply_offset,
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width=self.inv_inst[num].rx())
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# Add pins in two locations
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for xoffset in [in_xoffset, out_xoffset]:
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pin_pos = vector(xoffset, nand_pin.cy())
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self.add_power_pin(n, pin_pos)
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