mirror of https://github.com/VLSIDA/OpenRAM.git
31 lines
768 B
Python
31 lines
768 B
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2020 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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class _mirror_axis:
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def __init__(self, x, y):
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self.x = x
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self.y = y
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class _bitcell:
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def __init__(self, mirror, split_wl):
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self.mirror = mirror
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self.split_wl = split_wl
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class cell_properties():
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"""
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TODO
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"""
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def __init__(self):
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self.names = {}
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self._bitcell = _bitcell(mirror = _mirror_axis(True, False),
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split_wl = False)
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@property
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def bitcell(self):
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return self._bitcell
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