mirror of https://github.com/VLSIDA/OpenRAM.git
124 lines
4.6 KiB
Python
124 lines
4.6 KiB
Python
# See LICENSE for licensing information.
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#
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# Copyright (c) 2016-2019 Regents of the University of California and The Board
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# of Regents for the Oklahoma Agricultural and Mechanical College
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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#
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import debug
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import utils
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from tech import GDS, layer, parameter, drc
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import logical_effort
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import bitcell_base
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class bitcell_1rw_1r(bitcell_base.bitcell_base):
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"""
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A single bit cell (6T, 8T, etc.) This module implements the
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single memory cell used in the design. It is a hand-made cell, so
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the layout and netlist should be available in the technology
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library.
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"""
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pin_names = ["bl0", "br0", "bl1", "br1", "wl0", "wl1", "vdd", "gnd"]
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type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
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"INPUT", "INPUT", "POWER", "GROUND"]
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storage_nets = ['Q', 'Q_bar']
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(width, height) = utils.get_libcell_size("cell_1rw_1r",
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GDS["unit"],
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layer["boundary"])
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pin_map = utils.get_libcell_pins(pin_names, "cell_1rw_1r", GDS["unit"])
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def __init__(self, name=""):
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# Ignore the name argument
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bitcell_base.bitcell_base.__init__(self, "cell_1rw_1r")
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debug.info(2, "Create bitcell with 1RW and 1R Port")
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self.width = bitcell_1rw_1r.width
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self.height = bitcell_1rw_1r.height
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self.pin_map = bitcell_1rw_1r.pin_map
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self.add_pin_types(self.type_list)
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self.nets_match = self.do_nets_exist(self.storage_nets)
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def get_bitcell_pins(self, col, row):
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"""
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Creates a list of connections in the bitcell,
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indexed by column and row, for instance use in bitcell_array
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"""
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bitcell_pins = ["bl0_{0}".format(col),
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"br0_{0}".format(col),
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"bl1_{0}".format(col),
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"br1_{0}".format(col),
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"wl0_{0}".format(row),
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"wl1_{0}".format(row),
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"vdd",
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"gnd"]
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return bitcell_pins
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def get_all_wl_names(self):
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""" Creates a list of all wordline pin names """
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row_pins = ["wl0", "wl1"]
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return row_pins
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def get_all_bitline_names(self):
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""" Creates a list of all bitline pin names (both bl and br) """
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column_pins = ["bl0", "br0", "bl1", "br1"]
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return column_pins
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def get_all_bl_names(self):
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""" Creates a list of all bl pins names """
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column_pins = ["bl0", "bl1"]
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return column_pins
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def get_all_br_names(self):
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""" Creates a list of all br pins names """
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column_pins = ["br0", "br1"]
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return column_pins
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def get_read_bl_names(self):
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""" Creates a list of bl pin names associated with read ports """
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column_pins = ["bl0", "bl1"]
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return column_pins
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def get_read_br_names(self):
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""" Creates a list of br pin names associated with read ports """
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column_pins = ["br0", "br1"]
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return column_pins
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def get_write_bl_names(self):
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""" Creates a list of bl pin names associated with write ports """
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column_pins = ["bl0"]
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return column_pins
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def get_write_br_names(self):
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""" Creates a list of br pin names asscociated with write ports"""
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column_pins = ["br0"]
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return column_pins
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def get_bl_name(self, port=0):
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"""Get bl name by port"""
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debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
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return "bl{}".format(port)
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def get_br_name(self, port=0):
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"""Get bl name by port"""
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debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
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return "br{}".format(port)
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def get_wl_name(self, port=0):
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"""Get wl name by port"""
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debug.check(port < 2, "Two ports for bitcell_1rw_1r only.")
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return "wl{}".format(port)
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges to graph. Multiport bitcell timing graph is too complex
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to use the add_graph_edges function."""
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pin_dict = {pin: port for pin, port in zip(self.pins, port_nets)}
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# Edges hardcoded here. Essentially wl->bl/br for both ports.
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# Port 0 edges
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graph.add_edge(pin_dict["wl0"], pin_dict["bl0"], self)
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graph.add_edge(pin_dict["wl0"], pin_dict["br0"], self)
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# Port 1 edges
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graph.add_edge(pin_dict["wl1"], pin_dict["bl1"], self)
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graph.add_edge(pin_dict["wl1"], pin_dict["br1"], self)
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