mirror of https://github.com/VLSIDA/OpenRAM.git
DRC/LVS passing for all parameterized gates. Magic and GDS match for SCMOS rules again. |
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|---|---|---|
| .. | ||
| __init__.py | ||
| calibreDRC_scn3me_subm.rul | ||
| calibreLVS_scn3me_subm.rul | ||
| tech.py | ||