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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-03 08:27:11 +02:00
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4aee700331a2d07fe052e12c74b32329f74fe35d
OpenRAM/technology/scn3me_subm/mag_lib
T
History
Matt Guthaus 51a72e26c7 Fix via1 BL disconnect error.
2018-01-31 10:35:28 -08:00
..
cell_6t.mag
Fix via1 BL disconnect error.
2018-01-31 10:35:28 -08:00
ms_flop.mag
Add wells to fix DRC errors in SCMOS library cells.
2018-01-22 16:28:20 -08:00
replica_cell_6t.mag
Fix via1 BL disconnect error.
2018-01-31 10:35:28 -08:00
sense_amp.mag
Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments.
2018-01-24 13:02:55 -08:00
tri_gate.mag
Fixed bug with missing tri gate via.
2018-01-29 17:29:30 -08:00
write_driver.mag
Capitalize bitline labels in write driver
2018-01-24 13:15:14 -08:00
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