mirror of https://github.com/VLSIDA/OpenRAM.git
66 lines
2.2 KiB
Python
Executable File
66 lines
2.2 KiB
Python
Executable File
#!/usr/bin/env python3
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"""
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Run a regression test on a control_logic
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"""
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import unittest
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from testutils import header,openram_test
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import sys,os
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sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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class control_logic_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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import control_logic
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import tech
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# check control logic for single port
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debug.info(1, "Testing sample for control_logic")
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a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=32)
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self.local_check(a)
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# check control logic for multi-port
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OPTS.bitcell = "pbitcell"
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OPTS.replica_bitcell = "replica_pbitcell"
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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debug.info(1, "Testing sample for control_logic for multiport")
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a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8)
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self.local_check(a)
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# Check port specific control logic
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
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a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="rw")
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self.local_check(a)
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OPTS.num_rw_ports = 0
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OPTS.num_w_ports = 1
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debug.info(1, "Testing sample for control_logic for multiport, only write control logic")
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a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="w")
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self.local_check(a)
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 1
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debug.info(1, "Testing sample for control_logic for multiport, only read control logic")
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a = control_logic.control_logic(num_rows=128, words_per_row=1, word_size=8, port_type="r")
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self.local_check(a)
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globals.end_openram()
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# run the test from the command line
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if __name__ == "__main__":
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(OPTS, args) = globals.parse_args()
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del sys.argv[1:]
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header(__file__, OPTS.tech_name)
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unittest.main()
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