mrg 5b556e6ef5 Update unit test results with new Verilog models.

2021-04-15 15:48:20 -07:00

..

sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib

Update golden results with new lib syntax

2020-04-22 10:40:04 -07:00

sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib

Update golden results with new lib syntax

2020-04-22 10:40:04 -07:00

sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib

Update golden results with new lib syntax

2020-04-22 10:40:04 -07:00

sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib

Convert capital names to lower case for consistency

2019-08-21 13:45:34 -07:00

sram_2_16_1_freepdk45_TT_1p0V_25C.lib

Update golden results with new lib syntax

2020-04-22 10:40:04 -07:00

sram_2_16_1_freepdk45.lef

Add PDK layer names to tech file

2020-11-09 09:10:43 -08:00

sram_2_16_1_freepdk45.sp

Convert capital names to lower case for consistency

2019-08-21 13:45:34 -07:00

sram_2_16_1_freepdk45.v

Update unit test results with new Verilog models.

2021-04-15 15:48:20 -07:00

sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib

Update golden results with new lib syntax

2020-04-22 10:40:04 -07:00

sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib

Update golden results with new lib syntax

2020-04-22 10:40:04 -07:00

sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib

Update golden results with new lib syntax

2020-04-22 10:40:04 -07:00

sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib

Convert capital names to lower case for consistency

2019-08-21 13:45:34 -07:00

sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib

Update golden results with new lib syntax

2020-04-22 10:40:04 -07:00

sram_2_16_1_scn4m_subm.lef

Add PDK layer names to tech file

2020-11-09 09:10:43 -08:00

sram_2_16_1_scn4m_subm.sp

Convert capital names to lower case for consistency

2019-08-21 13:45:34 -07:00

sram_2_16_1_scn4m_subm.v

Update unit test results with new Verilog models.

2021-04-15 15:48:20 -07:00