Matt Guthaus 9a4b2b4341 Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

..

sram_2_16_1_freepdk45_analytical.lib

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

sram_2_16_1_freepdk45.lef

Revised LEF and Verilog generation. Does not read GDS for speed improvements.

2017-12-19 09:01:24 -08:00

sram_2_16_1_freepdk45.lib

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

sram_2_16_1_freepdk45.sp

RELEASE 1.0

2016-11-08 09:57:35 -08:00

sram_2_16_1_freepdk45.v

RELEASE 1.0

2016-11-08 09:57:35 -08:00

sram_2_16_1_scn3me_subm_analytical.lib

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

sram_2_16_1_scn3me_subm.lef

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

sram_2_16_1_scn3me_subm.lib

Rewrite the parameterized transistor and gate classes.

2017-12-12 15:04:01 -08:00

sram_2_16_1_scn3me_subm.sp

RELEASE 1.0

2016-11-08 09:57:35 -08:00

sram_2_16_1_scn3me_subm.v

RELEASE 1.0

2016-11-08 09:57:35 -08:00