OpenRAM

characterizer

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

gdsMill

Added new scmos test with a bigger design. Added error checks for not found label and not found pin shapes.

2017-05-24 10:50:45 -07:00

router

Improved router debugging and return error if unable to route.

2017-05-31 13:59:49 -07:00

tests

Merge branch 'router'

2017-06-05 09:08:17 -07:00

bank.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

bitcell_array.py

Analytical delay model from Bin Wu. Unit test not passing.

2017-05-30 12:50:07 -07:00

bitcell.py

Analytical delay model from Bin Wu. Unit test not passing.

2017-05-30 12:50:07 -07:00

calibre.py

Changed DRC and LVS results output database to end in .db instead of .results. Calibre uses file extensions to determine file type.

2017-04-21 14:07:16 -07:00

contact.py

Removed unique id for contacts. Contact/via name, however, must distinguish types of contacts based on layers used.

2017-04-26 10:24:51 -07:00

control_logic.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

debug.py

Add checks for valid OPENRAM_HOME and OPENRAM_TECH directories and subdirs

2017-05-12 14:56:31 -07:00

design.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

example_config_freepdk45.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

example_config_scn3me_subm.py

Modified default tech back to freepdk. Config file overrides command line.

2017-01-11 11:47:58 -08:00

geometry.py

Added zoom to technology file so labels in each tech are readable size. Made default size.

2017-05-23 16:18:11 -07:00

globals.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

hierarchical_decoder.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

hierarchical_predecode2x4.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

hierarchical_predecode3x8.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

hierarchical_predecode.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

hierarchy_layout.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

hierarchy_spice.py

Analytical delay model from Bin Wu. Unit test not passing.

2017-05-30 12:50:07 -07:00

lef.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

logic_effort_dc.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

ms_flop_array.py

Analytical delay model from Bin Wu. Unit test not passing.

2017-05-30 12:50:07 -07:00

ms_flop.py

Analytical delay model from Bin Wu. Unit test not passing.

2017-05-30 12:50:07 -07:00

nand_2.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

nand_3.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

nor_2.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

openram.py

Modify banner to output temp path

2016-11-15 10:14:04 -08:00

options.py

Made back-annotation and analytical modelling boolean options. Default is false.

2017-05-31 08:12:17 -07:00

path.py

Improve debug messages. Remove add_inst for via in wire.

2016-11-18 14:10:30 -08:00

pinv.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

precharge_array.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

precharge.py

Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules.

2017-04-26 14:33:03 -07:00

ptx.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

regress.sh

Add regress.sh script for convenience

2016-11-18 08:00:34 -08:00

replica_bitcell.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

replica_bitline.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

route.py

Fixed rotated via bug. May still have a via-to-via spacing problem.

2017-04-24 13:47:56 -07:00

sense_amp_array.py

Analytical delay model from Bin Wu. Unit test not passing.

2017-05-30 12:50:07 -07:00

sense_amp.py

Analytical delay model from Bin Wu. Unit test not passing.

2017-05-30 12:50:07 -07:00

single_level_column_mux_array.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

single_level_column_mux.py

Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules.

2017-04-26 14:33:03 -07:00

sram.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

tri_gate_array.py

Analytical delay model from Bin Wu. Unit test not passing.

2017-05-30 12:50:07 -07:00

tri_gate.py

Analytical delay model from Bin Wu. Unit test not passing.

2017-05-30 12:50:07 -07:00

utils.py

Updated gdsMill with new getter routines for router to get by location. Cleaned up vlsiLayout.

2017-05-17 14:27:14 -07:00

vector.py

Merge master branch into router

2017-01-09 14:04:37 -08:00

verilog.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

wire.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

wordline_driver.py

Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.

2017-06-02 11:11:57 -07:00

write_driver_array.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

write_driver.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00