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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
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3bcb79d9d5bf6a32d2ea703785eef74681f2ddb5
OpenRAM/compiler/characterizer
T
History
jsowash 3bcb79d9d5 Removed code for RW ports to not precharge on writes. Previously, the entire bitline was written where part was an old value and part was the wmask value.
2019-07-24 15:01:20 -07:00
..
__init__.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
charutils.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
delay.py
Added wmask valuesto functional test through add_wmask()
2019-07-23 15:58:54 -07:00
functional.py
Removed code for RW ports to not precharge on writes. Previously, the entire bitline was written where part was an old value and part was the wmask value.
2019-07-24 15:01:20 -07:00
lib.py
Reapply jsowash update without spice model file
2019-06-24 08:59:58 -07:00
logical_effort.py
Fix space before comment
2019-06-14 08:43:41 -07:00
measurements.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
model_check.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
setup_hold.py
Fix space before comment
2019-06-14 08:43:41 -07:00
simulation.py
Added wmask valuesto functional test through add_wmask()
2019-07-23 15:58:54 -07:00
stimuli.py
Merged and fixed conflicts with dev
2019-06-25 16:55:50 -07:00
trim_spice.py
Fix space before comment
2019-06-14 08:43:41 -07:00
worst_case.py
Fix space before comment
2019-06-14 08:43:41 -07:00
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