Logo
Explore Help
Sign In
luke/OpenRAM
Watch 1
Star 0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 09:30:38 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
37fffb2ed2320e4908fd88272f2e9fe509d3dc0a
OpenRAM/compiler/bitcells
T
History
mrg e2602dd79b Add comments for pins. Fix noconn in dummy pbitcell.
2019-07-16 17:30:31 -07:00
..
bitcell_1rw_1r.py
Port name maps between bank and replica array working.
2019-07-15 11:29:29 -07:00
bitcell_1w_1r.py
Port name maps between bank and replica array working.
2019-07-15 11:29:29 -07:00
bitcell.py
Port name maps between bank and replica array working.
2019-07-15 11:29:29 -07:00
dummy_bitcell_1rw_1r.py
…
dummy_bitcell_1w_1r.py
…
dummy_bitcell.py
…
dummy_pbitcell.py
…
pbitcell.py
Add comments for pins. Fix noconn in dummy pbitcell.
2019-07-16 17:30:31 -07:00
replica_bitcell_1rw_1r.py
…
replica_bitcell_1w_1r.py
…
replica_bitcell.py
…
replica_pbitcell.py
…
Powered by Gitea Version: 1.27.2 Page: 5576ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API