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mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-29 17:39:02 +02:00
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369aa85cd2787037eacfeccfda9668d7be1d41db
OpenRAM/technology/scn3me_subm/gds_lib
T
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Matt Guthaus 1dc7752429 Fix 6T and replica cell contact spacing issues with Magic DRC.
DRC/LVS passing for all parameterized gates.
Magic and GDS match for SCMOS rules again.
2018-01-26 12:39:00 -08:00
..
cell_6t.gds
Fix 6T and replica cell contact spacing issues with Magic DRC.
2018-01-26 12:39:00 -08:00
ms_flop.gds
Add wells to fix DRC errors in SCMOS library cells.
2018-01-22 16:28:20 -08:00
replica_cell_6t.gds
Fix 6T and replica cell contact spacing issues with Magic DRC.
2018-01-26 12:39:00 -08:00
sense_amp.gds
Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments.
2018-01-24 13:02:55 -08:00
tri_gate.gds
Duplicate gnd label on metal1 pin in tri gate.
2018-01-24 13:20:34 -08:00
write_driver.gds
Capitalize bitline labels in write driver
2018-01-24 13:15:14 -08:00
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